ALtera推荐的两段式状态机的写法

陈飞龙 · 发表于 2017-11-1 19:48:20

Verilog-2001 State Machine
module verilog_fsm (clk, reset, in_1, in_2, out);
input clk, reset;
input [3:0] in_1, in_2;
output [4:0] out;
parameter state_0 = 3'b000;
parameter state_1 = 3'b001;
parameter state_2 = 3'b010;
parameter state_3 = 3'b011;
parameter state_4 = 3'b100;
reg [4:0] tmp_out_0, tmp_out_1, tmp_out_2;
reg [2:0] state, next_state;
always @ (posedge clk or posedge reset)
begin
if (reset)
state <= state_0;
else
state <= next_state;
end
always @ (*)
begin
tmp_out_0 = in_1 + in_2;
tmp_out_1 = in_1 - in_2;
case (state)
state_0: begin
tmp_out_2 = in_1 + 5'b00001;
next_state = state_1;
end
state_1: begin
if (in_1 < in_2) begin
next_state = state_2;
tmp_out_2 = tmp_out_0;
end
else begin
next_state = state_3;
tmp_out_2 = tmp_out_1;
end
end
state_2: begin
tmp_out_2 = tmp_out_0 - 5'b00001;
next_state = state_3;
end
state_3: begin
tmp_out_2 = tmp_out_1 + 5'b00001;
next_state = state_0;
end
state_4:begin
tmp_out_2 = in_2 + 5'b00001;
next_state = state_0;
end
default:begin
tmp_out_2 = 5'b00000;
next_state = state_0;
end
endcase
end
assign out = tmp_out_2;
endmodule

陈飞龙 · 发表于 2017-11-1 19:49:36

An equivalent implementation of this state machine can be achieved by using ‘define instead of
the parameter data type, as follows:
‘define state_0 3'b000
‘define state_1 3'b001
‘define state_2 3'b010
‘define state_3 3'b011
‘define state_4 3'b100