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在项目中用了双口RAM,单独编译RAM时仿真结果正确,将RAM用在项目中编译时出现如下错误提示:
Error: WYSIWYG primitive "ram_block1a0" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a0" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a1" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a1" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a2" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a2" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a3" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a3" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a4" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a4" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a5" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a5" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a6" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a6" must have Port A, Address port or parameter specified
Error: WYSIWYG primitive "ram_block1a7" must use clk0 port
Error: WYSIWYG RAM primitive "ram_block1a7" must have Port A, Address port or parameter specified
在网上查的出现这种错误可能是没有给RAM加时钟信号,但是我已经给RAM加过时钟信号了,为什么还出现这种错误提示呢?盼解答。 |
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