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FALCON-E25TG FPGA development Platform ISE Process experiment manual
Version 3.1, November 2011
FALCON-E25TG Type FPGA development platform
Ise Process Experiment Manual
Experimental 1:xilinx Ise tool flow Experiment P02-P14
Experimental 2:architecture Wizard and pin distribution experiment P15-P27
Experiment 3: Global timing constraint Experiment P28-P40
Experiment 4: Comprehensive technical Experiment p41-p49
Experimental 5:IP Nuclear generator system experiment p50-p57
Experimental 6:chipscope Debugging Experiment p58-p69
 
Experimental 1:xilinx ISE tool flow Experiment
Target board: Falcon-E25TG
Introduced
Describes the basic usage flow of the ise™ tool through the sample program.
This experiment is suitable for users to understand and verify the knowledge after learning the design process of ISE tool and the principle of Picoblaze microcontroller.
Goal
After completing the sample experiment, you will have the following capabilities:
 Create a new project
 familiar with FPGA design basic process
 Master the basic technical features of Picoblaze
Lab Preparation
1. Copy the Labs-materials/ise-flows folder on the disc to the D: root directory. Or unzip the Ise_flows.rar directly under the CD Labs-materials directory to the D: root directory.
2. Connect the JTAG interface of the computer with the port and the FALCON-E25TG experimental board by downloading the cable.
3. Connect one end of the RS232 serial line to the computer, and the other end is connected to the RS232 port of FALCON-E25TG.
Note: In each of the following experiments, follow this preparation.
Steps
Experiment 1 is done mainly through the following four steps:
 Create a new project
 Add source program files for the project
 Design Simulation (Simulation)
 Design Implementation (Implementation)
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step.
If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
 
Step 1: Start
View the 8-bit microcontroller Picoblaze document and familiarize yourself with its structure and instruction set. This experiment uses Picoblaze interrupt application as ISE design process use case, it is necessary to learn picoblaze structure and instruction set, but not necessary.
Picoblaze user manual kcpsm3_manual.pdf stored in D:\ Ise-flows \ labs \ LAB1 \ Verilog (or vhdl) \ KCPSM3 \ docs\ directory.
Open ISE Project Navigator to create a new project.
1. Select "Start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator" (or double-click the desktop Xilinx ISE Design Suite 12.4 icon directly ), start Ise Project Navigator.
2. In the Project Navigator interface, select the File→new Project menu or choose directly to do the upper part of the icon and open the new project Wizard (Figure 1-1).
3. Through "..." button to browse the following directory, and then click on the list.
Verilog User: D:\ Ise-flows \ labs \ LAB1 \ Verilog
VHDL User: D:\ ise-flows \ labs\ lab1 \ VHDL
Figure 1-1. Create a new Project wizard
 
4. Under Name, enter Flow_lab.
5. Click Next.
6. The Device Properties dialog box appears (Figure 1-2).
Figure 1-2. Device Properties dialog box
7. After selecting the options below, click Next:
device family:spartan3e
device:xc3s250e
package:tq144
speed Grade:–4
synthesis tool:xst (Vhdl/verilog)
simulator:ise Simulator (Vhdl/verilog)
preferred Language:verilog or VHDL (select the language you use)
8. The dialog box appears as shown in the following illustration, click Finish (Figure 1-3).
 
Figure 1-3. Project Summary dialog box
Add HDL source files to the project.
9. Click Project–add Copy of Source or click on the right toolbar to browse to D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \vhdl (or Verilog) folders.
10. Select the Kcpsm3_int_test and kcpsm3 files under the VHDL or Verilog folder and click Open.
11. Click Next and click Finish. The following dialog box (Figure 1-4) appears, indicating that you have chosen correctly.
12. Click OK to accept the default settings.
Figure 1-4. Adding Source Files dialog box
 
Figure 1-5. Sources Window in Project Navigator
Note: There is a small red question mark in front of the Program-int_test module in Figure 1-5. This is because the top-level file kcpsm3_int_test.vhd/v contains an illustrated statement of the int_test.vhd/v module that has not yet been added to the current project. The int_test.vhd/v module is used to generate a picoblaze command memory ROM (using 1 Blockram-generated ROM). Step 2 discusses the generation of the instruction memory ROM.
Step 2: Generate instruction Memory
In this experiment, Picoblaze's assembly application has been written and stored in the INT_TEST.PSM file (Note: Learning this program contributes to the understanding of the experiment). Compiling this file using the Picoblaze's own assembler will result in a int_test.vhd file, a int_test.v file, and an instruction memory output file such as Int_test.coe. Depending on the language used in the selection of one of the first two files into the current design top-level file (kcpsm3_int_test), the integrated tool can automatically push (infer) out of the picoblaze instruction memory (Rom generated by 1 blockram). In addition, using the third file Int_test.coe, the picoblaze instruction memory can also be illustrated by the Coregenerator tool.
1. Open Windows Browser and browse to D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \ Assembler folders.
Note: KCPSM3.exe assembly tools, 3 Rom_form template files, and two. PSM assembly source files are all in this directory (Figure 1-6). When the compilation is complete, all output files also appear in this directory.
Figure 1-6. Compiling catalog Content
2. Open the INT_TEST.PSM file using a text editor. Refer to (ug129) Picoblaze 8-bit Embedded microcontroller User Guide and KCPSM3 manual to understand the source program. (These reference documents are in D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \ Documents subdirectory)
 
3. Open the DOS command window. ("Start  program xilinx design Suite 12.4accessoriescommand Prompt")
4. Use the CD command to browse to the assembler directory (Figure 1-7).
D:\ Ise-flows \ labs \ LAB1 \ Vhdl\KCPSM3\Assembler
or d:\ Ise-flows \ labs \ LAB1 \ Verilog\KCPSM3\Assembler
Figure 1-7. Command Window
5. Enter the assembly code below the command prompt (Figure 1-7), which will automatically produce the instruction memory output file.
KCPSM3 INT_TEST.PSM
Note: init_test.vhd (VHDL language program for generating instruction Memory), INT_TEST.V (Verilog language program for generating instruction memory) and Init_ can be seen in the current directory. Test.coe (an initialization data file for the Coregenerator tool to generate instruction memory). In fact, all three files are stored in the machine code generated after the application is compiled, and the user can open the three files and view the binary machine code portion of the system.
6. In ISE Project Navigator, Projectadd Copy of Source found in directory path D: \ ise-flows \ labs \ lab1 \ vhdl \KCPSM3 \ Assembler Int_test.vhd or INT_TEST.V file. (Fig. 1-8)
Figure 1-8. Add a int_test.vhd file to the current project
 
7. Click Open and click OK. In this way, we add the Init_test.vhd or INIT_TEST.V file to the current project. (Fig. 1-9)
Figure 1-9. Hierarchical view of Picoblaze design
Note: The top-level file kcpsm3_int_test.vhd/v contains an example statement of the int_test.vhd/v module. Therefore, after adding the source code int_test.vhd/v to the current project, the small red question mark in front of the program module disappears, that is, the program module is no longer an "empty box" in the current project. (Figure 1-9)
Step 3: Behavior simulation
In step 3, the user adds TESTBENCH.VHD/.V code to the current project, uses the Xilinx ISIM emulator to complete the behavior simulation (behavioral simulation), and examines the simulation results. The TESTBENCH.VHD/.V code is a simulation test bench file, which describes the generation of input excitation for the test module and the processing of the output results, which cannot be used for comprehensive implementation. In this experiment, the TESTBENCH.VHD/.V file has been written and can be used directly. In the user's own design, you need to write this file yourself.
1. In Ise Project Navigator, click Projectadd Copy of Source, point to D:\ Ise-flows \ labs \ LAB1 \ VHDL (or Verilog) \ KCPSM3 \ vhdl (or Verilog) directories.
2. Select the Test_bench.vhd or TESTBENCH.V file and click Open.
Figure 1-10. Select Test_bench.vhd (or testbench.v) file
3. As shown in Figure 1-10, click OK and the test bench.vhd file is added to the current project.
 
4. As shown in Figure 1-11, select Set to simulation in the view window.
Figure 1-11. Sources Window containing test bench
5. As shown in Figure 1-12, click test_bench.vhd/v in the Sourcese window to display the Xilinx ISE Simulator toolbar in the Processes window. Click the plus sign in front of the toolbar, right-click the simulator behavioral Model, select Properties, and open the Properties dialog box. As shown in Figure 1-13, enter 10000ns at simulation run time, click the OK button, and close the Properties dialog box.
Figure 1-12. Show Xilinx ISE Simulator toolbar in Processes window
 
Figure 1-13. Setting simulation Properties
6. Double-click the simulate behavioral Model to simulate the behavior of the design. Click the window to enlarge the icon, select the name bar in the waveform window, right-click Radix-hexadecimal, you will see three interrupt pulses and their interrupt values, the simulation results waveform shown in the following figure (Figure 1-14).
Figure 1-14. Isim Behavior Simulation Results
7. Use the magnification tool in the toolbar to enlarge the simulation results graph to confirm that the simulation results are correct.
Note: in D: \ ise-flows \ labs\ lab1 \ vhdl \ KCPSM3 \ Assembler directory, the file Int_test.log records the address and machine code of each instruction in the instruction memory, and the user can verify the correctness of the simulation results against this file. 。
8. Close the simulation window to end the simulation.
Step 4: Implementation of the design
Step 4 implements the design.
 
1. As shown in Figure 1-15, in the Sources window of the project, select implementation and click the top-level file kcpsm3_int_test.vhd/v of the project.
Figure 1-15. Sources window
2. As shown in Figure 1-16, in the Processes window, double-click Implement Design.
Figure 1-16. Processes for source window
3. Expand the plus sign before implement DESIG and you will see three steps to implement it. After each step runs, a small icon appears before the step to indicate the completion of the step. The icon indicates as follows:
Indicates that the procedure completed successfully
Indicates that the procedure is complete but has a warning message
Indicates that the action step was not completed due to an error
Note: During the implementation process, the message window at the bottom of Project Navigator displays the various messages generated by the implementation process in real time.
 
4. When each action step is complete, a corresponding report is generated that contains the details that are generated during the step run. These reports can be accessed directly in the detailed reports section of the Design Summary window in the Ise Project Navigator, or by clicking the appropriate command under the steps in the Processes window. As shown in Figures 1-17, 1-18, 1-19.
Figure 1-17. Design Summary Window General Information
Figure 1-18. Resource utilization information in the Design Summary window
 
Figure 1-19. Access various reports in the detailed reports section of the Design Summary window
Conclusion
In Experiment 1, we completed the main steps of the ISE design: Creating a project, adding source files, simulation design, and design implementations.
In Experiment 2, we will learn to review various design reports, analyze designs, and check whether the area and performance metrics of the design meet the requirements.
 
Experimental 2:architecture Wizard and pin distribution experiment
Target board: Falcon-E25TG
Introduced
This paper introduces the PIN allocation tool of Structure Wizard and Planahead and its application.
Goal
After completing this experiment, you will be able to:
1. Configure a DCM component using the Structure Wizard
2. Example of DCM components into the design
3. Assign pin position using Planahead
4. Perform design confirmation pin allocation
5. Download to hardware for testing
Design Overview
Experiment 2 uses the UART real-time clock (real-time clock) module to complete a band on the FALCON-E25TG board that can view and set the time via HyperTerminal? Heart seed any neon stool pen our unitary low field art real-time clock module and its use documents can be found in the free Picoblaze distribution package.
This system is designed to achieve real-time clocks with hours, minutes and seconds, and has the ability to set alarm clocks. The system uses HyperTerminal software to set up, view time information and alarm clock information through UART serial message.
Some simple ASCII commands will be used in the experiment. When the "KCPSM3>" prompt appears in the HyperTerminal window, you can send action commands to the Development Board system via the keyboard. The wrong action command will have a "syntax error" message on the HyperTerminal, and the "Invalid Time" message will appear at the wrong time setting. If the command transfer is faster than the design processing (such as accepting the cache to fill), the "Overflow error" message will appear (which is unlikely to happen, of course).
The system requires a working clock of $ MHz. Because the FALCON-E25TG board only provides a clock of $ MHz, you need to use the Structure Wizard (architecture Wizard) to sample the DCM module and output the $ MHz working clock.
Steps
This example consists mainly of four parts:
1. Configure DCM using the Structure wizard;
2. Example of DCM to vhdl/verilog design;
3. Assign pin position;
4. Implement the design, download the design, verify the design through the Development Board.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step.
If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: Configure DCM using the Structure Wizard Architecture Wizard
Open the existing project.
1. Select start → All Programs →xilinx ise design Suite12.4→ISE design Tools→project Navigator, into the ISE Project Navigator environment;
2. Select File→open Project and point to the following directory to select Arwz_pace.xise to open the project;
Verilog users:d:\ise_flows\ labs\ Lab2\verilog\arwz_pace
VHDL users:d:\ise_flows\ labs\ Lab2\vhdl\arwz_pace
The design does not yet have an example of the DCM module. The following steps use the Structure Wizard to configure a DCM with an input clock of 50MHz and an output clock of 55MHz.
1. Select Projectnew Source.
2. In the source window that opens, select IP (Coregen architecture Wizard) and enter MY_DCM as the file name.
Figure 2-1 Selecting IP (Coregen architecture Wizard)
3. Click Next.
 
4. Expand FPGA Features and designclockingspartan-3e in the Select IP Type window, Spartan-3A, and select single DCM SP v12.1i. (Fig. 2-2)
Figure 2-2. Architecture Wizard Selection Box
5. Click Next and click Finish.
6. In the Xilinx clocking wizard–general Setup window, set the following options (Figure 2-3):
clk0, CLKFX and LOCKED: choosing
rst Box: Not selected
input lock Frequency: Fill in $ MHz
 
Figure 2-3 Xilinx clocking wizard–general Setup window
Note: The input frequency is indicated in clocking Wizard, and the Structure Wizard automatically configures DCM's operating mode (high frequency mode or low frequency mode). Based on the input clock frequency, the Structure wizard can calculate whether the required output frequency is within the allowed range. In addition, if the CLKFX output is selected, the Structure Wizard calculates the output frequency size of the CLKFX and estimates the clock jitter.
7. Click Next.
8. In the Xilinx clocking Wizard–clock buffers window (Figure 2-4), select the default value and click Next.
Figure 2-4 Xilinx clocking wizard–clock buffers window
9. Fill in 55MHz under the "Output Frequency of the Xilinx clocking wizard–clocking Frequency Synthesizer dialog box. (Fig. 2-5)
 
Figure 2-5 Specifying DCM output frequency
10. Click the Finish button to see My_dcm.xaw added to the current project in the Sources window of the project, but not to the file hierarchy of the top-level design module, which requires the next example (Figure 2-6).
Note: If you do not see My_dcm.xaw in the Sources window of the current project at this time, you can add it manually through Projectadd source. (Fig. 2-6)
Figure 2-6 lists DCM in the design hierarchy
 
Step 2a: Example of DCM to Verilog design
Note: VHDL users skip this step,? Benzene hard Comfort Street? b
All necessary files required for the current project have been created, and step 2a will be an example of the DCM module in the top-level design. Experiment 2 completes the example by copying the relevant content in the sample template and then pasting it in the top-level design.
1. In the Sources window, double-click uart_clock.v to open the source code.
2. In the Sources window, select My_dcm.xaw. Double-click View HDL instantiation Template in the Processes window, and the sample template for the MY_DCM module opens in the editor on the right. In the example template (file Form My_dcm.tfi), copy the Component Declaration section (under the//instantiate the module annotation) and paste it under the UART_CLOCK.V Insert DCM//here note in component code;
3. The MY_DCM port connection signal in the experiment does not use the system default name, need to modify the MY_DCM port connection signal, the specific modification please refer to the following code (you can also copy and paste the following code into the UART_CLOCK.V code//Insert DCM Below the component here Note).
MY_DCM INST_MY_DCM (
Clkin_in (CLK),
Clkfx_out (Clk55MHz),
Clkin_ibufg_out (),
CLK0_OUT (),
Locked_out (lock));
4. Define DCM's 55MHz output connection signal under annotation//signals for DCM:
Wire clk55MHz;
Note: At this point, the UART_CLOCK.V design has been updated and all clock signals have been renamed to the new Clock (clk55MHz).
5. Add the lock output port to the top-level entity:
Module Uart_clock (TX, RX, Alarm, CLK, Lock)
Output TX;
Input rx;
Output alarm;
Input CLK;
Output lock;
Note: The lock output port will drive the LD0 light of the FALCON-E25TG board. When hardware is debugged, the LD0 light indicates that DCM has successfully implemented the clock lock.
6. Click File→save to save the file. At this point, the module My_dcm.xaw is plugged into the correct location at the top-level design module file hierarchy. (Fig. 2-7)
 
Step 2 B: Example of DCM to VHDL design
Note: Verilog users skip this step!
All necessary files required for the current project have been created, and step 2b will be an example of the DCM module in the top-level design. Experiment 2 completes the example by copying the relevant content in the sample template and then pasting it in the top-level design.
1. In the Sources Project window, double-click Uart_clock.vhd to open the source code.
2. In the Sources window of the project, select My_dcm.xaw, double-click View HDL instantiation Template in the Processes window, and the sample template file (My_dcm.vhi) is opened. In the HDL-only template file, copy the component declaration (from component MY_DCM to end component) and paste it into the UART_CLOCK.VHD code annotation statement-Insert DCM Component Declaration below here;
3. Modify the port connection signal according to the following code, or copy and paste the following code into the annotation statement in UART_CLOCK.VHD code-Insert DCM component instantiation below).
Inst_my_dcm:my_dcm
PORT MAP (
Clkin_in => CLK,
Clkfx_out => Clk55MHz,
Clkin_ibufg_out => Open,
CLK0_OUT => Open,
Locked_out=> lock);
4. Under the annotation statement--signals for DCM, define the DCM output connection signal for DCM:
Signal clk55mhz:std_logic;
Note: The UART_CLOCK.VHD design has been updated. All clock signals have been renamed to the new Clock (clk55MHz).
5. Add the lock output port to the top-level entity:
Entity Uart_clock is
Port (
Tx ut std_logic;
Rx:in std_logic;
Alarmut std_logic;
Clk:in std_logic;
Lockut std_logic);
End Uart_clock;
Note: The lock output port will drive the LD0 light of the FALCON-E25TG board. When hardware is debugged, the LD0 light indicates that DCM has successfully implemented the clock lock.
6. Click File→save to save the file. At this point, the module My_dcm.xaw is plugged into the correct location at the top-level design module file hierarchy. (Fig. 2-7)
 
Figure 2-7. Hierarchical diagram of design files after routine completion
Step 3: Assign pin position
Steps 1 and 2 complete the design of adding DCM modules. The input and output ports of the FPGA need to be assigned to the pin position before the design implementation is carried out. In this step you will use the Planahead tool for pin allocation.
1. In the hierarchy window of the project, select the top-level design file UART_CLOCK.VHD/.V.
2. In the Processes window of the project, expand User Constraints and double-click Io-pin Planning (planahead)-pre-synthesis to open planahead.
Note: When asked if you have added a UCF file to the project, click "Yes".
3. If the Introduction window appears, click Close to turn it off.
Note: For VHDL users, 8 errors may be reported, ignoring them because they are not produced by design.
4. Select the CLK signal in the I/O Ports window, type p54 in the position box in the I/O Ports Properties window, and then click Apply. Select the Configure option, and then select LVCMOS33 as the interface standard. Other numbers are performed in a similar way (refer to the Lab2_ucf.txt file under D:\ISE_FLOWS \ UCF folder, and the FPGA pin position corresponding to the I/O port appears after "LOC ="). As shown in Figure 2-8 (Configure the constraint view of the pins).
CLK: 50MHz Crystal Vibration connected to the Development Board
lock: Connect the LD0 lamp on the Development Board
alarm: Connect the LD1 lamp on the Development Board
RX: Serial data receiving PIN for MAX3232 chip connected to the Development Board
TX: Serial data sending pins connected to the MAX3232 chip on the Development Board
 
Figure 2-8: Pin constraint view
5. Select a pin (such as CLK) in the I/O ports window and click the Fit Selection button to display the device and encapsulated view of the selected Pin, as shown in Figure 2-9.
6. Click File-save Design to save the pin assignment.
7. Click File-exit Exit Planhead and click OK.
 
Figure 2-9. Device and Package view
8. Click the Uart_clock file in the Sources window, expand user Constraints in the Processes window, double-click Edit Constraints (Text), and observe through Planahead in Uart_ The constraint file generated in CLOCK.UCF. Observe the text content of the UCF file and confirm that the PIN assignment is correctly written to the constraint file. It was observed that there was an error in the path name of the UCF file, as shown in Figures 2.10 and 2.11.
Figure 2.10 Before modification
 
Figure 2.11 After modification
Step 4: View the run report and set up HyperTerminal
Implement the design, view the report report, and confirm that the PIN allocation meets the requirements. Set up HyperTerminal.
1. In the Sources window of the current project, select the top-level design file UART_CLOCK.VHD/.V.
2. In the processes window of the current project, expand implement Design, and then expand the place in the Back-annotate Route to expand the Pin locations.
3. Double-click the View Locked Pin Constraints (Project Navigator automatically decides which programs need to run and the report is turned on when they are finished running).
4. Review the run report to see if the pin allocation completed in step 3 is implemented correctly.
5. Open HyperTerminal. The steps are: Start  program  attachments  communication  HyperTerminal.
6. Take a name for HyperTerminal and click OK. Specifies that COM1 is a port connection.
7. Set the following parameters for the port. Then click OK to complete the settings (Figure 2-12).
 digits per second: 38400
 Data bits: 8
 Parity: None
 Stop bit: 1
 Data flow control: None
 
Figure 2-12. Serial Port Communication settings
8. Select the File menu in the HyperTerminal window, click the Properties button, select Settings, click ASCII code settings, select the check box to attach the line break to the end of the incoming line (Figure 2-13). Click Confirm to complete the property settings.
Figure 2-13. ASCII settings for serial port connections
 
Step 5: Download the design
Generate a download bitstream (bitstream) file and download it to the FPGA.
1. Connect the power adapter, Jtag download line and serial communication cable for the FALCON-E25TG Development Board, and turn on the FALCON-E25TG Development Board power switch.
2. Select the top-level file UART_CLOCK.VHD/.V, double-click Generate programming file, and produce a bitstream file that can be downloaded to the FPGA.
3. When the bitstream file is generated, expand generate programming file and double-click Manage Configuration Project (impact).
4. Click the Initialize Chain button, point Yes, browse to the project catalog selection Uart_clock.bit
Figure 2-14. JTAG chain with configurable files assigned
5. In the impact window, right-click xc3s250e, select Program, and click OK in the Programming Options dialog box. Configure the Bitstream file to start downloading to the FPGA if the download successfully appears in program Succeeded.
Note: After the download is successful, a kcpsm3> prompt appears in the HyperTerminal. (If the kcpsm3> prompt does not appear, move the cursor inside the HyperTerminal and press the BACKSPACE key)
Figure 2-15. Super Terminal display window
Step 6: Run the Urat real-time clock
Commands are issued to the system through HyperTerminal to verify the correctness of the design. You can refer to the manual for detailed instructions. (Manual for Uart_real_time_clock.pdf)
 
1. After entering the "time" command after the kcpsm3> prompt, enter the current clock in HH:MM:SS format in the HyperTerminal (Figure 2-16);
Figure 2-16. Display the current time
2. When you enter the "alarm" command after the command prompt, the current set alarm (alarm) time is displayed in hh:mm:ss form. Note that the alarm feature is turned off at this point (Figure 2-17).
Figure 2-17. Display alarm time and status
3. Enter the "alarm on" command after the command prompt and the alarm (alarm) function is turned on.
4. After entering "alarm 00:00:30" after the command prompt to set the alarm time 30 seconds, enter "Time 00:00:00" set the current time, 30 seconds later, the LD1 light on the board lit.
5. Enter the "alarm off" command after the command prompt and the LD1 light goes off.
Conclusion
In this experiment, you use the Structure Wizard Architecture Wizard to configure the DCM module and sample it into the current design. Use Planahead to assign the pin position of the IO port. Finally, implement and download the design and complete the verification in the hardware.
 
Experiment 3: Global timing constraint experiment
Target board: Falcon-E25TG
Introduced
Experiment 3 learns to use global timing constraints to improve the working clock frequency of the design.
Experiment 3 learns to analyze design performance using Post-map static Timing the Post-place and Post-place&route static Timing.
Goal
After completing the experiment, you will be able to:
 Enter global timing constraints using Xilinx Constraints Editor
 Observe the reasonable index of timing constraint of Post-map Static Timing
 For each timing constraint, use the Post-place and Route Static Timing to view the critical path
Design Overview
In the Xilinx development environment, the constraints of implementing the pre-input are called logical constraints, and logical constraints are saved in the UCF file. Users can create and edit UCF constraint files directly, but they need to be familiar with the syntax of UCF files and the naming of components such as triggers, networks, and PD in the design, while using the constraint editor (Constraints Editor) to create and modify constraints can reduce requirements and increase efficiency.
Experiment 3 hardware design principle as shown in Figure 3-1, is a picoblaze system with UART peripherals.
Figure 3-1. Picoblaze system
The main task of this experiment is to implement a loop test (loopback test) system with Picoblaze assembly language programming. The Loop test system first sends a signal to a device, and then returns a signal from the device to test that the device is working properly.
As shown in Figure 3-1, the system input ports are:
 
CLK Clock signal (50Mhz oscillation signal on FALCON-E25TG Development Board)
RST Reset Signal
RS232_RX Serial input
SWITCHES[7:0] 8-bit's switch input
The output ports are:
Rs232_tx Serial output
LEDS[7:0] 8-bit LED output
Experiment 3 through the Development Board of the LED lamp to receive the signal sent by the switch, the toggle switch can be seen on the corresponding LED lamp on the light. In addition, the system's UART TX module sends data to the computer, and the system's UART RX module receives the data sent back by the computer.
The software program can correctly perform two loopback functions: in the LED lamp response switch settings, RS232 serial port receiving port response to the sending port serial data.
Once the experiment is complete, you will be able to understand how to design a simple embedded handler using Picoblaze.
Timing report Information
The timing report details why timing constraints fail and which paths are critical paths.
Timing Analyzer (Timing Analyzer) produces time series reports. The timing analyzer interface consists of three windows (Figure 3-2).
Use the hierarchical browser on the left (hierarchical Browser) to browse through the various parts of the report.
The path details (path Detail) window on the right includes a detailed description of the timing report.
The window at the top right shows the item selected in the hierarchical browser. The contents of the project are displayed in the Path Detail window.
Figure 3-2. The Timing Analyzer GUI
The Path Details window (Figure 3-3) includes detailed information about path latency, including:
slack: The difference between the constraint value (that is, the required path delay value) and the actual path delay value (the negative number indicates that the actual delay is greater than the constraint value, that is, the requirement is not met)
 
Source and end points of  Path
Detailed composition list of  path latency
Fan out of each network in the  Delay path (fanout)
 Path Delay sum
A percentage example of  logical latency and network latency (this value indicates whether your latency path is reasonable).
Figure 3-3. Detailed Path Analysis
Steps
In Experiment 3, you will build a simple embedded system and improve performance with global timing constraints. The main steps are as follows:
1. Compilation of a Picoblaze project.
2. Enter the global timing constraint.
3. Enter the PIN constraint file.
4. Implement the design and analyze the time series report.
5. Write software and run HDL simulation.
6. Hardware validation.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: Compile the program template
Open the Time_const project in ISE Project Navigator, compile the source program PROGRAM.PSM, and generate program.vhd/v files for generating instruction memory.
 
1. Select start → program →xilinx ise design Suite 12.4→ISE design tools→project Navigator to enter the ISE Project Navigator environment.
2. Select File→open Project and point to the following directory, select Time_const.xise, open the project;
Verilog User: D:\ISE_Flows\ labs\ lab3\verilog\time_const
VHDL User: D:\ISE_Flows\ labs\ lab3\vhdl\time_const
3. Select start → program → accessories → command prompt, open the DOS command window, and use the CD command to point to the Assembly compiler directory:
The D:\ISE_Flows CD \labs\lab3\verilog\Assembler (Verilog user)
The CD d:\ISE_Flows\ labs\ lab3\vhdl\Assembler (VHDL user)
4. After entering the assembler directory, enter the: KCPSM3 PROGRAM.PSM command after the DOS command prompt symbol. When the command is complete, a number of files are generated under assembler, including the VHDL file (PROGRAM.VHD) and the Verilog file (PROGRAM.V), which are used for synthesis (integrated out of program memory ROM) and simulation.
5. Add the program.vhd/v file to the current project.
6. Click the top-level file loopback.vhd/v in the Project Sources window, and then double-click Check Syntax in the Synthesis-xst directory in the Processes window to see if there is a syntax error.
7. In the behavioral Simulation model, TESTBENCH.V/VHD is used as a simulation test platform for simulation. The time is 35000ns.
Note: After zooming in on the simulation waveform, you can see results similar to the following figure. Hexadecimal 55 represents the input signal of the switch, but there is no output on the LED light. In a later experiment, the code will be edited so that the LED light responds to the switch settings.
Figure 3-4 The switch position is not reflected on the LEDs
Step 2: Enter global timing constraints
Step 2 uses the constraint editor input cycle (PERIOD) and offset input/output (OFFSET in/out) constraints.
1. In the hierarchy window of the project, select the top-level file loopback.vhd/.v
2. In the Processes window under the Sources window, expand User constaraints and double-click Create tming Constraints (Figure 3-5). If there are no related constraint files in the current project directory, Project Navigator automatically creates a constraint file.
3. Click Yes to create a new UCF file: LOOPBACK.UCF, add it to the project.
 
4. Open the Constraint editor and select the lock domains under Constraint type (Figure 3-6).
Figure 3-5 Processes window of the project
Figure 3-6 Global Timing Constraint Editor
Set the cycle (PERIOD) constraint of the global clock signal CLK is 20ns
5. Double-click CLK under Unconstraints Lock to open the Lock Period dialog box. (Fig. 3-7)
6. Click OK to accept the default value (20ns).
Set the input bias constraint (OFFSET in) value of the global clock signal CLK is 7ns and the output bias constraint (OFFSET out) value is 7.5 ns. Save the constraint and exit the constraint editor.
7. Select the inputs below the Constraint Type window, double-click the blank area next to the Unconstraint port column to open offset in wizard, and leave the default settings to select Next. (Fig. 3-8)
 
8. Enter the constraint value of 7 ns in the blank area shown in Figure 3-9. Click OK. (Fig. 3-9)
9. Select the outputs below the Constraint Type window, double-click the blank area next to the Unconstraint port column to open offset in wizard, and leave the default settings to select Next. Enter the constraint value for 7.5 ns in the blank area shown in Figure 3-10. Click OK. (Fig. 3-10)
NOTE: The above constraints appear in the window in the lower-left corner of the constraint editor. (Fig. 3-10)
Figure 3-7 Clock Cycle dialog box
 
Figure 3-8 OFFSET in Wizard–clock Edge Page
Figure 3-9. OFFSET in Constraint dialog box
Figure 3-10. OFFSET out Constraint dialog box
 
Step 3: Enter pin position constraints
Step 3 Specifies the pin position for the top-level design I/O port. In this example, pin allocation is completed by directly copying the pin position in the given text file to the UCF file.
1. Expand User Constraints Double-click Edit Constraints (Figure 3-11) to open the UCF file.
Figure 3-11. Open the UCF file
2. Open D:\ Ise_flows \ lab3_ucf.txt file.
Figure 3-12. Pin position constraints
3. Copy the constraints in the Lab3_ucf.txt file to the UCF file.
4. Save and close the UCF file.
Step 4: Design timing Analysis
Implementation (implement) design. View the Post-map static Timing and Post-place of the 2 Route static Timing, analyze the design timing, and complete tables 1 and.
 
1. In the Processes window, expand implement Design to further expand the map.
If you don't see implement Design, verify that the loopback.vhd/.v file in the source window is selected.
2. Expand Generate post-map Static Timing.
3. Double-click Analyze Post-map static Timing to open the Static Time series Analysis tool (Timing Analyzer) to see the timing after the MAP.
Use the Post-map Static Timing reporting to check that the timing constraints in this example are feasible to avoid wasting place in the time of the
Locate the period constraint of clkfx_buf (DCM output) in the report and complete the problem ①.
If the time series constraint is not found in the Post-map static Timing, right-click Post-map static Timing to select Rerun all.
① problem-Complete the following table:
Chart 1 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint
Post-map
4. Close the timing Analyzer window.
5. In the Processes window, expand the place of the place of the generate and the post-place of the Timing.
6. Double-click the post-place of the Timing Route static Timing, open the Static Time series Analysis Tool (Analyzer), view the timing after the Place&route, and complete the problem ②.
② problem-Complete the following table:
Chart 2 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint
Post-p&r
Note: If the design does not meet the timing requirements after the place of the place of the following route, the constraint will need to be relaxed and implemented.
Step 5: Write a program to perform HDL emulation
With the actions of the previous steps, the hardware has met the timing requirements.
 
Step 5 Develop the Picoblaze assembler to meet the software requirements. The application template, including the definition of a large number of constants, has been given in the experiment. In this experiment, the user only needs to write simple code to complete three tasks (task), of which task #3 is the hardest. Experiment 5 only needs to complete Task #1,task #1完成开关和灯的回路测试.
It is important to note that each time you change the code, you must re-compile it to generate a new instruction memory.
1. Locate the PROGRAM.PSM in the assembler directory, write the code to complete the task #1, implement the read switch status and write to the LED light control port. Recompile once.
Tip: You only need to write two lines of code (refer to the KCPSM3 User manual). If you can't complete the code successfully, you can refer to the appropriate file in Labsolutions.
2. Go to behavioral Simulation mode and double-click Simulate behavioral model
3. Analyze the output waveform and close the simulation window when you are finished. (Fig. 3-13)
Figure 3-13. LEDs the setting signal of the response switch
 
Note: Binary value 10101010 (hexadecimal AA) appears in the Picoblaze switches input port and, after a delay, appears on the LED light output port. The simulation console (Sim console) Displays the simulation success information. (Fig. 3-14)
Figure 3-14. Observe information in the Simulation console
Step 6: Generate platform Flash PROM file
The FALCON-E25TG experimental board is equipped with Xilinx xcf02s/xcf04s platform Flash PROM. Step 6 uses the Impact tool to generate the Prom programming bitstream file (Intel formatted MCS format).
1. Double-click Generate programming file in the Processes window to generate the FPGA download bitstream file.
2. Start the Ipact tool, double-click the Create PROM file, and select each option as shown in the following figure. (Fig. 3-15)
Figure 3-15. Set up prom file formats
3. Click OK and finish to add Loopback.bit. When the dialog box appears, click No. This no longer adds additional FPGA bitstream files (1 Prom support configuring multiple FPGAs).
 
4. Double-click Generate file ... to generate PROM with bitstream files (MCS files), and if successful, you can see the " ROM File generation succeeded" message. (Fig. 3-16)
Figure 3-16. Generate MCS files
Step 7: Configure Prom to run the loopback experiment
Step 7 selects the prom and FPGA to be configured separately by selecting configuration mode, and the loopback program is tested on the Development Board.
1. Place the Development Board configuration mode selector switch in JTAG mode and turn on the Development Board power supply. (See FALCON-E25TG Board Manual)
2. Double-click Boundary-scan. This is shown in Figure 3-17.
Figure 3-17. Select Boundary Scan in impact
 
3. In the Boundary Scan window of impact, right-click the white area and select Initialize Chain.
4. When asked XC3S250E's configuration bitstream file, click Bypass.
5. Add the. mcs file to xcf02s/04s Platform Flash.
6. Right-click xcf02s/04s in the Jtag chain and select program. When the Programming Properties dialog box appears, click Ok>.
Note: If the program is unsuccessful, do not select the Erase before programming option, and then re-program.
7. Place the Development Board configuration mode selector switch in m-s mode, press the Prog button of the Development Board, or re-power, and the Development Board will configure the FPGA from the prom. Toggle the switch, you can see the corresponding LED lights on the light.
Conclusion:
This experiment uses Xilinx Constraints Editor to enter the global timing constraint to analyze the design timing by looking at Post-map and post-place of the Timing.
Timing constraints meet performance requirements. When implementing the first layout cabling of a tool, it is necessary to determine whether the timing constraints of the design are feasible. Timing performance can be estimated based on the Post-map Static Timing. Determine whether the timing requirements are met by looking at the post-place of the Route Static Timing.
Answer
The answer is not unique, and the results are related to factors such as the software version, patch version, and operating system used in the experiment.
① problem-Complete the following table:
Chart 1 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint ~18.18 NS 7 NS 7.5 NS
Post-map ~8.85 NS ~7.115ns ~3.76 NS
② problem-Complete the following table:
Chart 2 PERIOD constraint OFFSET in constraint OFFSET out constraint
Constraint ~18.18 NS 7 NS 7.5 NS
Post-p&r ~13.78 NS ~6.89 NS ~4.54 NS
 
Experiment 4: Comprehensive technology Experiment
Target board: Falcon-E25TG
Introduced
Synthesis is an important link in the design process of FPGA/CPLD, and the advantages and disadvantages of the combined results directly affect the final layout wiring results. A good complex can make the user's design occupy the smallest physical area of the chip, and the fastest operating frequency, which is an important index to evaluate the advantages and disadvantages of the complex.
Synplify/synpliy Pro is a comprehensive tool produced by Synplicity company, which has attracted much attention for its comprehensive speed and excellent optimization. Xilinx Synthesis XST is a comprehensive tool embedded in the ISE software by Xilinx, although it is not prominent and functionally comprehensive compared to the industry's popular integrated tools such as Synplify/synpliy Pro, But Xilinx has the best knowledge of its FPGA/CPLD internal structure, so XST support for Xilinx devices is also the most direct and effective. More importantly, XST is embedded in the ISE, can be used directly, there will be no other costs.
Experiment 4 describes higher performance in the Xilinx FPGA design process by using the XST comprehensive options (attributes).
Goal:
After completing the experiment, you will be able to:
 uses comprehensive options such as keep hierarchy and fanout to improve aggregate results and improve design performance.
 Modify XST Comprehensive options, read the XST synthesis report, and judge the quality of the comprehensive results.
Steps:
This experiment consists of the following four parts:
 View hardware and complete application software design
 is combined according to the default values for the comprehensive option
 Change Comprehensive options
 View the combined results in RTL.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: View the composition of the design hardware and complete the application software
Open Ise™project Navigator and open the project file synth_lab.ise.
1. Select start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator, open Xilinx ISE.
2. Select File→open Project, select Synth_lab.xise, click Open
 
verilog User: D:\ISE_Flows\ labs\ lab4\verilog\synth_lab
VHDL User: D:\ISE_Flows\ labs\ lab4\vhdl\synth_lab
Update the PROGRAM.PSM file in Experiment 3 to complete task #2 (Task 2 Displays the words "Xilinx Rules" on the screen), which is compiled and added to the current project.
3. Open PROGRAM.PSM (in the Assembler subdirectory of this experiment) and add code to complete task #2.
Tip: At the top of the program, all ASCII characters are listed as constants. There are only two instructions (load and output) to display a single character. If the encoding is difficult, you can refer directly to the corresponding file in Labsolutions.
4. Open the Command window and browse to the assembler directory. The directory contains the PROGRAM.PSM file that you just encoded.
5. Enter the following command at the DOS prompt, the assembler compiles the application PROGRAM.PSM, and the resulting file is used to generate the instruction memory.
KCPSM3 PROGRAM.PSM
Note: If the PROGRAM.V (or. vhd) file is already in the current project. You can remove it before reloading the newly generated file into the project.
Step 2: Synthesize and implement according to the default values
Synthesis of top-level file Loopback.v/.vhd
1. Click Loopback.v/.vhd
2. In the Processes window, double-click synthesize-xst
Review the comprehensive report and answer questions ① and ② in the Sources window.
3. In the Design Overview window, click View Synthesis
4. Using the Find tool at the bottom of the page, enter timing Summary and press ENTER.
① write down the estimated clock frequency (for comparison with later results):
____________________________
5. Enter device utilization in Find and click Find Next.
② Write down Resource usage:
Slices
Slice Flip Flops
4 input LUTs
Iobs
Brams
Global Clocks
DCMs
 
6. Closure of the comprehensive report.
7. In the Process window, expand implement Design and expand place in the place of the place.
Double-click Analyze Timing/floorplan Design (planahead), the Web table view is opened, and you can observe it through tools→show hierarchies loopback Hierarchical relationships with two modules of primitives (figures 4-1 and 4-2)
8. Exit Planahead.
Figure 4-1. Nets and Primitives View
Figure 4-2. A flat view of the physical layer, the network table, and the design
 
Step 3: Change the comprehensive options
In general, HDL Design is a collection of modules at all levels. Maintaining the hierarchy of the module or leveling the hierarchy (flattened) is beneficial to the design to some extent and requires specific analysis of specific problems. For FPGAs, if you can pay attention to the synchronization design techniques, choose to maintain the design of the hierarchy to improve performance, easy to debug analysis. In some cases, especially in the asynchronous circuit design, the hierarchical structure of the leveling design can allow the comprehensive tool to optimize the design better.
Sometimes, the effect of synthesizing by default value is not good. Designers need to understand the common comprehensive options, flexible application.
Change the comprehensive options, as shown in the following figure, and then synthesize them once.
keep Hierarchy:yes
Figure 4-3. Synthetic attributes
1. In the Processes window, right-click synthesize select Properties.
2. In Synthesis Options, set Keep hierarchy to Yes, as shown in Figure 4-3.
Note: If you select Keep hierarchy (in fact, a comprehensive constraint is specified), the implementation tool retains the design hierarchy throughout the implementation process (referring to VHDL entities or Verilog modules, rather than the macros that was extrapolated during the synthesis process).
3. Click OK and re-synthesize.
4. Open the synthesis report, enter the timing Summary in the find below the page, press ENTER to find the relevant Time series summary section, answer the following question.
③ recorded the estimated clock frequency and observed changes in system performance.
__________________________
 
5. Enter device utilization in the find below the page, click Find Next, and find the Resource Utilization section to answer the following question.
④ the utilization of resources is recorded in the following table:
Slices
Slice Flip Flops
4 input LUTs
Iobs
Brams
Global Clocks
DCMs
6. Enter Fanout in Find and click Find Next.
⑤ which NET has the largest fanout? Which data path does it belong to?
_______________________________
Fanouts is too big to cause cabling problems, and by xst constraints, you can limit the number of fanout. This restriction does not require special consideration, especially when its number is less than 30.
7. Right-click synthesize–xst Select Properties.
8. In the Xilinx Specific options option, enter the max fanout number 50. Click OK. (Fig. 4-4)
9. Double-click Synthesize–xst and re-synthesize.
10. Open the synthesis, find fanout, and answer the question below.
⑥ which net Fanout is the largest and which data path does it belong to?
___________________________
11. In the synthesis, find timing summary and answer the following questions.
What is the maximum clock frequency for ⑦ design?
___________________________
 
Figure 4-4. Xilinx Specific Options
12. In the Processes window, expand implement design and double-click Analyze Timing/floorplan Design (planahead) below place in the place.
13. View the design hierarchy (hierarchy) through Tools→show hierarchy. (Fig. 4-5 and fig. 4-6)
Figure 4-5. Network table Design view
 
Figure 4-6. Hierarchical view of the design
Step 4: Download and system testing
Step 4 produces the FPGA configuration Bitstream file and configures the FPGA through the JTAG download line.
1. Configure the configuration mode selection jumper on the Falcon Development Board and select the configuration mode as JTAG.
2. Connect the download line and power the Falcon board.
3. Open the HyperTerminal created in Experiment 3 (the baud rate is 9600).
4. Double-click Generate programming to generate a bitstream file.
5. Expand configure target device and double-click Manage Configuration project (impact)
6. When the Impact dialog box appears, select Boundary-scan Mode, click Next, and then click Finish.
7. The prompt box that appears indicates that the impact software detects two devices and clicks OK.
8. Assign the Loopback.bit file to the XC3S250E device (the first device in the JTAG chain) and select bypass for the platform Flash Prom device.
9. Right-click the xc3s250e device and select Program.
Note: After the download is successful, you should see the words "Xilinx Rules" in the HyperTerminal window.
10. Toggle the switch, on the Falcon board can see the LED light lit.
 
Conclusion
The comprehensive option is actually the constraint imposed on the synthesis, with different comprehensive options, and the performance of the integrated system is different. Understanding mastering the comprehensive availability of options can help improve system design performance.
Answer
① writes down the estimated clock frequency (for comparison with later results).
Minimum period (Verilog): one ns (Maximum Frequency: ~107 MHz) Minimum period (VHDL): ~8.15 NS (Maximum Frequency: ~122 MH Z
Note: The experimental results are related to the PC system you are using
② Write down Resource usage:
Slices 163 (Verilog)/160 (VHDL)
Slice Flip Flops 147 (Verilog)/147 (VHDL)
4 Input LUTs 303 (Verilog)/299 (VHDL)
IOBs 21 （Verilog and VHDL）
Brams 1 (Verilog and VHDL)
Global Clocks 2 (Verilog and VHDL)
DCMs 1 (Verilog and VHDL)
③ record estimated clock frequency to observe system performance changes
Minimum period (Verilog): ~9.76 NS (Maximum Frequency: ~102 MHz)
Minimum period (VHDL): ~8.68 NS (Maximum Frequency: ~115 MHz)
Note: The experimental results are related to the PC system you are using
④ record resource utilization in the following table
Slices 167 (Verilog)/163 (VHDL)
Slice Flip Flops 147 (Verilog)/147 (VHDL)
4 Input LUTs 303 (Verilog)/298 (VHDL)
Iobs (Verilog and VHDL)
Brams 1 (Verilog and VHDL)
Global Clocks 2 (Verilog and VHDL)
DCMs 1 (Verilog and VHDL)
 
⑤ which NET has the biggest fanout? Which data path does it belong to?
Verilog
LUT3:I2->O (Operand_select_mux_1 (port_id<1>)) with Fanout of 84
Data path:my_kcpsm3/reg_loop_register_bit_1 to Transmit/buf_0/register_bit_3
Vhdl
LUT3:I2->O (Reg_loop[0].operand_select_mux (port_id<0>)) with Fanout of 84
Data Path:my_kcpsm3/reg_loop[0].register_bit to Transmit/buf/count_width_loop[3].register_bit
⑥ which net Fanout is the largest and which data path does it belong to?
Verilog
LUT3:I2->O (Operand_select_mux_1 (port_id<1>)) with Fanout of 43
Data path:my_kcpsm3/reg_loop_register_bit_1 to Transmit/buf_0/register_bit_3
Vhdl
LUT3:I2->O (Reg_loop[0].operand_select_mux (port_id<0>) with Fanout 43
Data Path:my_kcpsm3/reg_loop[0].register_bit to Transmit/buf/count_width_loop[3].register_bit
What is the maximum clock frequency for ⑦ design?
Minimum period (Verilog): ~11.7.ns (Maximum Frequency: ~85 MHz)
Minimum period (VHDL): ~10.6 NS (Maximum Frequency: ~94 MHz)
Note: The experimental results are related to the PC system you are using
 
Experimental 5:IP nuclear generator system experiment
Target board: Falcon-E25TG
Introduced
Experiment 5 generates IP cores through the Xilinx core generator™ system and embeds them into user design.
Goal
When the experiment is complete, you will be able to acquire the following abilities:
 generates an IP core with Xilinx core generator
 of IP core to HDL design
 Behavior Simulation of HDL design with IP kernel
 Design through Development Board hardware verification
Steps
Experiment 5 uses the core generator generator to generate the program memory of Picoblazer, and picoblaze it into the application system, and finally completes the hardware verification on the FALCON-E25TG Development Board.
 View hardware design, build program memory ROM initialization file
 Generator Memory IP kernel (blockram)
 Process Memory IP kernel to application system
 The behavior simulation of application system
 Hardware validation on the Development Board
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Step 1: View the hardware design, build the program memory ROM initialization file
Start the Ise™project Navigator and open the project file
1. Select start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator, open Xilinx ISE 12.4.
2. Click File→open Project, select Coregen.xise, and click Open.
verilog Users: Browse d:\ Ise_flows \ labs\ Lab5\verilog\coregen
VHDL Users: Browse d:\ Ise_flows \ labs\ Lab5\vhdl\coregen
 
Browse the design and you can see a red question mark mark. Using the program of the previous experiment, complete the task #3, and the assembly generates a parameter file with the. Coe (Coe used to initialize the program memory ROM).
3. In D:\ ISE_Flows\Labs\lab5\vhd (Verilog) \assembler Open the assembly application PROGRAM.PSM in the directory.
4. Write the program code, complete the task #3, tasks 3 through the HyperTerminal to display the content entered from the keyboard.
Note: Refer to the comments in your code when writing your code. If you have difficulty writing code, refer to the appropriate content in solutions.
5. Open the DOS Command Prompt window and enter the following command at the command prompt:
KCPSM3 PROGRAM.PSM
Note: The assembler will produce included. Several files, including the Coe file. In the use of core generator to generate instruction memory ROM. The Coe file is used to initialize ROM data.
Step 2: Generator memory IP kernel (blockram)
Create a source file of type IP Core, named program. This source file (IP Core) will use Blockram.
1. In the Processes window, select Project→new Source.
2. In the New Source dialog box, select IP (Coregen architecture Wizard) and enter the program in the file Name blank. (Fig. 5-1)
Figure 5-1. New Source dialog box
3. Click Next.
4. In the Select Core Type dialog box, expand Memories Storage Elements, expand Rams ROMs, and select Block Memory Generator v4.3. (Fig. 5-2)
Figure 5-2. Select the Kernel Type dialog box
 
5. Click Next and click Finish.
Note: After 1-2 minutes, the CORE generator™ system interface opens.
6. As shown in Figure 5-3, set the dual Port Block memory parameter according to the following parameters, click Next.
 Component Name: Program
 Storage Internal type: Dual Port ROM
 Memory Size: 1024 x 18
Figure 5-3. Block Memory Options
7. Set the port a parameter as shown in Figure 5-4 and click Next.
read width:18
read depth:1024
operating Mode:write First
enable:always Enabled
 
Figure 5-4. Port A Options
8. Click Load Init file to select the Program.coe file you just generated. (Fig. 5-5)
Figure 5-5. Initialize memory with program
 
Note: If the. Coe file format is not compatible (the specified file is red), you can use the text editor to modify the. Coe file, keep only the file rows (2) that begin with Memory_initialization, and then rerun the load Init file step.
9. Click the Show button, select Memory_initialization_vector from the drop-down box, and you can observe the initialization data of the program memory, as shown in Figure 5-6, and then click OK. When the FPGA configuration is complete, these initialization data is loaded into the Blockram as the program memory.
Figure 5-6. Block RAM Initialization Content
10. Click Next and click Finish.
Note: The Program.xco file should have been automatically added to the current project.
Step 3a: Example program memory IP kernel into the application system (Verilog)
Note: VHDL users do not do this step, please skip directly to step 3b
The program memory ROM kernel generated in step 2 is analyzed.
1. In the Sources window, double-click LOOPBACK.V and the Loopback.v file is opened in the right window.
2. Select program in the hierarchy of the Project window, and then double-click View HDL instantiation Template (Figure 5-7a)
Figure 5-7a. Examples of templates
3. Copy and paste the annotation statement of the sample template content to the loopback.v file under "//instantiate the ROM block here".
 
4. Edit the illustrated statement in the LOOPBACK.V file as follows to complete the signal connection:
Program My_program (
. Clka (Clk55MHz),
. Addra (Address),
. Douta (instruction),
. CLKB (1 ' b0),
. ADDRB (A ' b0000000000),
. DOUTB ());
5. Select File→save.
Step 3b: Example program memory IP kernel into the application system (VHDL)
Note: Verilog users do not do this step, please skip directly to step 4
The program memory ROM kernel generated in step 2 is analyzed.
1. In the Hierarchy window, double-click Loopback.vhd and the source file is opened in the right window.
2. Select program in the hierarchy of the Project window, and then double-click View HDL instantiation Template (Figure 5-7b)
Figure 5-7b. Language Templates
 
3. Copy and paste the component declaration content into the Loopback.vhd file in the sample module. Paste the annotation statement into the Loopback.vhd file--insert component declaration for Pro.
4. Copy and paste the component instantiation content into the Loopback.vhd file in the sample module. Paste the annotation statement into the Loopback.vhd file-insert component instantiation for program here.
5. Edit the illustrated statement in the Loopback.vhd file as follows to complete the signal connection:
My_program:program
Port Map (
Clka => Clk55MHz,
Addra => Address,
Douta => Instruction,
Clkb => ' 0 ',
ADDRB => "0000000000",
DOUTB => Open);
6. Select File→save Save.
Step 4: Simulate the behavior of the application system
Check the Testbench file to understand what has changed.
1. In the Hierarchy window, double-click TESTBENCH.V/.VHD (if not, add it yourself by referring to the preceding steps).
To view the features of Testbench, note the following comments section:
the Testbench Toggles switches
waits for some lock cycles
checks the LEDs to see if they match the switch settings
2. In the Hierarchy window, select Program.xco.
3. In the Processes window, expand Coregen and double-click View VERILOG/VHDL functional Model.
Note: This file comes from the Xilinxcorelib simulation Experiment Model Library, which is automatically called when behavioral simulation is performed within the ISE. (For VHDL users, if the simulation model file does not appear, right-click View VERILOG/VHDL functional Model, select Open Without Updating)
Run behavior simulation with a simulation time of 50000 NS. Observe the simulation waveform and verify that the IP core has been properly embedded.
4. In the design window, select Simulation and select Testbench.v/.vhd.
5. In the Processes window, expand Isim Simulator and double-click Simulate Behavioral Model.
6. Enter 50000NS in simulation run time.
7. Click OK.
 
8. Double-click Simulate Behavioral Model.
9. Observe the simulation waveform and analyze whether the change of the LED light port signal can reflect the setting of the switch port signal.
Step 5: Hardware validation on the Development Board
Open HyperTerminal. Generate FPGA configuration bitstream files and download them to the lab board.
1. According to experiment 2, introduce a new super terminal, set the Super terminal baud rate of 9600, connect the development Board, turn on the power supply.
2. In the Processes window, expand Configure Target Device and double-click Manage Configuration Project (IMPACT).
3. When the impact window opens, the window shows two devices detected in the JTAG chain, click OK.
4. Assign loopback.bit files to the Spartan-3 xc3s25e device, and the rest select Bypass.
5. Right-click Spartan-3 xc3s250e, select program, click OK, will be configured with the JTAG download line FPGA.
6. After the download is successful, you will see "Xilinx rules!" in the HyperTerminal window , enter any character on the keyboard and observe the display in the HyperTerminal window.
Figure 5-9. Observe the output in the HyperTerminal window
Conclusion
Experiment 5 through the core generator™system generator memory IP kernel, and the example into the design. Veo and VHO files are examples of modules that can be used to easily automate the operation of IP cores. V and. VHD files are simulation modules that support the behavior simulation of IP cores.
 
Experimental 6:chipscope Debugging experiment
Target board: Falcon-E25TG
Introduced
Experiment 6 is on-chip debugging by embedding the Ila/icon kernel in the design.
Chipscope Pro (Online logic Analyzer) has the function of a traditional logic analyzer and is an in-chip signal analysis tool for Xilinx FPGA. Chipscope Pro reads the FPGA signal online and in real time through the JTAG port.
Depending on the trigger conditions set by the user, Chipscope Pro can save the signal that the user cares about in real time to the unused in-chip blockram, and then transfer it through the JTAG port to the analysis tool running on the computer, showing the time series waveform on the computer screen. The Chipscope Pro tool makes the FPGA no longer a black box, using Chipscope Pro to easily observe all the signals inside the FPGA, which is very beneficial for the internal logic debugging of the FPGA.
Use Chipscope Pro to observe the advantages of FPGA internal signals as follows:
 Low cost: Just a JTAG cable and Chipscope Pro software.
 Flexibility: The number of observed signals and storage depth is determined by the number of Blockram remaining in the device, and the more remaining Block-ram, the greater the number of observable signals and storage depth.
 Easy to use: Chipscope Pro is able to read design network tables (NGC, EDF, or edn files) and automatically insert itself (Web tables) into the original Design network table. Users can easily select the signal to be observed and can set complex trigger conditions. Chipscope Pro uses only a small number of lookup table resources and register resources, with little impact on the original design.
Goal
After completing the experiment, you will be able to:
 creates a Chipscope-pro source file in the Ise.
 uses Chipscope-pro to create ILA and ICON cores and to visualize them in the design.
 Use Chipscope Analyzer to set trigger options.
 Download the FPGA configuration bitstream file in Chipscope Analyzer.
 runs the on-chip debugging function to observe the waveform in Chipscope Analyzer.
Steps:
Experiment 6 modifies the Picoblaze software application and uses Chipscope-pro to run on-chip debugging.
The experiment consisted mainly of 4 steps:
 Add Chipscope Engineering files to current design
 Modify the ILA parameter and connect the signal
 Configuration Chipscope Analyzer software, update design
 run on-chip debugging functions.
Under the guidance of the Experimental Manual, you will complete the whole experiment step by step. If you are already familiar with the ISE software design process, you can skip the detailed instructions in one step and complete the experiment yourself.
Note: The symbol-guided paragraph is a description of the following steps in the paragraph, not an action step.
All steps in the handout that require the user to operate are guided by lowercase Arabic numerals.
Design Overview:
Experiment 6 uses Chipscope-pro to insert the icon core and Ila core into the current design, and the trigger port of the ILA kernel is the feedback of the UART_RX and UART_TX module signals in the design. Next, with HyperTerminal text input, you can set up triggers to capture data. When the buffer is full, you should see the results on the chipscope.
Step 1: Add Chipscope Engineering files to the current design
Open Ise™project Navigator and open the project file.
1. Select start → program →xilinx ise design suite 12.4→ise Design Tools→project Navigator, open Xilinx ISE.
2. Select File→open Project
verilog User: Browse to D:\ISE_Flows\ labs\lab6\ verilog\chipscope
VHDL Users:: Browse to D:\ISE_Flows \labs\lab6\ vhdl\chipscope
3. Select Chipscope.xise Click Open.
Create a Chipscope-pro project through Project Navigator.
4. Select Projectnew Source, open the Create Xinyuan file dialog box, click Chipscope Definition and Connection file, enter the file name Loopback_cs. Click Next. (Fig. 6-1)
 
Figure 6-1. Xinyuan file dialog box
5. In the Sources window, select the loopback file as the source file, click Next, and then click Finish. The Chipscope-pro source file is added to the sources of the Project window. (Fig. 6-2)
Figure 6-2. Add Chipscope definition and Connection (. CDC)
Step 2: Modify the ILA core parameter and connect the signal
Insert ICON and ILA cores into the current design network table. Connect the output of the accumulator to the input of the trigger and the ILA core.
1. Double-click the LOOPBACK_CS.CDC file to open the Chipscope-pro project (Inserter interface). (Fig. 6-3)
 
Figure 6-3. Chipscope-pro Core Inserter
Note: The Chipscope-pro project holds related source files, target files, kernel parameters, and kernel settings.
2. Click Next, click the new ILA Unit button in the lower-right corner, or select the new ILA Uni command under the Edit menu. Note that U0:ila appears in the upper-left window. (Fig. 6-4)
Figure 6-4. Embed the new Integrated Logic Analyzer (ILA) unit
 
3. Click Next to start setting the trigger parameters.
Each ILA or ILA/ATC core has 16 separate trigger ports that can be set separately. The trigger port is the bus structure, which consists of a separate signal or a bit bit ranging from 1 to 256. Each trigger port can connect 1 to 16 matching units.
Each matching unit is actually a comparator, connected to a trigger port, respectively, to detect events that trigger the port. One or more matching units are combined to form a complete trigger condition event that is used to control data capture. The ILA and ILA/ITC cores support 6 different types of matching units, and different matching units perform different comparison functions.
In Experiment 6, the ILA core is set by some UART control signals.
4. After setting the ILA trigger parameter according to the following data, click Next. (Fig. 6-5)
Trigger input and Match unit settings:
number of input Trigger Ports:3
Trigger Port Trigger Width # match Units counter Width match Type
TRIG0 1 1 Disabled Basic
TRIG1 1 1 Disabled Basic
TRIG2 1 1 Disabled Basic
Trigger Condition Settings:
enable Trigger Sequencer: Selected (used to specify the order in which events can be triggered)
max of Sequencer Levels:2
Storage Qualification Condition Settings:
enable Storage Qualification: Selected (for specifying which data to store)
Figure 6-5. Specifying Trigger Parameters
The maximum value of the sampled data that the ILA core can store in the sampling buffer is called the storage depth (data depth). Storage depth and data width are mutually constrained, depending on the size of the remaining blockram in the design.
5. Set the options below and click Next. (Fig. 6-6)
data depth:512
sample on:rising Lock Edge
data Same as Trigger port:unchecked
data Width:8
Figure 6-6. Specify Trigger Parameters
Net Connections connects the ILA or ILA/ATC nuclei to the selected signal. Users need to specify clocks, triggers, and data connections, respectively. No connection will display red. (Fig. 6-7)
Figure 6-7. Unconnected Net Connections
6. Click the Modify Connections button to appear in the Select Net interface. (Fig. 6-8)
 
Figure 6-8. Net Connections
The Select Net dialog box provides a simple graphical interface that connects the selected observation signal to the ILA or ILA/ATC core. By using the structure/nets of the upper-left window, you can browse the hierarchy of the current design, making it easy to select the signals you want to observe.
7. Select the Lock Signals tab under NET selections, click the CL signal in the list of networks on the left, and then click the Make Connections button in the lower right corner to connect the Clk55mhz signal to the clock port of the ILA core. (Fig. 6-9)
Figure 6-9. Connecting clock signals
8. Click the Trigger Signals tab to connect three trigger ports. (Fig. 6-10)
tp0:data_present (the signal indicates that the data appears in the UART_RX module)
tp1:read_from_uart (This is the input signal for the UART_RX module, indicating that the read operation will occur)
tp2:write_to_uart (This is the input signal for the UART_TX module, indicating that the write operation will occur)
Figure 6-10. Even contact with the starter port
 
9. Click the Data Signals tab to connect the Picoblaze data output port Out_port to the ILA kernel data port, as shown in Figure 6-11, and then click OK.
Figure 6-11. Connect the Picoblaze output port
10. Note that the lock port, the trigger port, and the data port under the Net Connections window all display black, indicating that all connections are valid. Click Return to Project Navigator to save the file. (Fig. 6-12)
Figure 6-12. Connect design with ILA core
Step 3: Configure Chipscope Analyzer software to update the design
The Chipscope-pro Analyzer tool is connected to the ILA core via the icon core. You can configure the FPGA through Chipscope-pro Analyzer, select the trigger conditions, set up the console, observe the capture data, and so on. There are several ways to work with captured data.
1. In the Hiersrchy window, click the top-level file Loopback.v/vhd, double-click Analyze Design Using chipscope in the Processes window, and open the Chipscope Analyzer tool.
2. Connect the FALCON-E25TG board download line and turn on the power supply on the board.
3. Click the open cable/search JTAG Chain button in the upper-left corner of the Chipscope Analyzer window. (Fig. 6-13)
Figure 6-13. Establish a JTAG connection
4.2 devices can be found in Jtag chain, namely spartan-3e xc3s250e and platform Flash xcf02s or xcf04s, click OK.
 
5. Right-click xc3s250e and select Configure.
6. Click Select New File, browse to the current project catalog, select Loopback.bit, and notice that. cdc files are also added to the project at the same time, click OK.
The Chipscope Pro Analyzer interface consists of four parts.
Each chipscope Pro ILA, ILA/ATC, and IBA cores have their own trigger settings window, which provides graphical interface setting triggers. The trigger structure of each Chipscope Pro core can be modified in real time without the need for a re-integration implementation. The trigger structure has three elements:
match Functions: Defines the comparison value for each matching cell.
trigger Conditions: Defines the full trigger condition based on a binary equation or a sequence of one/more matching functions.
capture Settings: Defines the number of sampled data, the number of sampling windows, and the position of triggers in the sampling window.
Experiment 6 Sets the trigger at the Picoblaze output to capture the text data it emits.
Figure 6-14. Chipscope Analyzer window
7. Specify the following Match Units. (Fig. 6-15)
radix: Binary
m0:triggerport0 (data_present): Value 1
m1:triggerport1 (Read_from_uart): Value 1
m1:triggerport1 (Write_to_uart): Value 1
 
Figure 6-15. Set up matching units
8. Click the area under Trigger condition equation, select the options below the Sequencer tab, generate the M0→M1 expression, and then click OK.
Figure 6-16. Trigger condition equation
9. Click on the area near storage qualification, select and equation, click M2, click OK. In this way, when the write_to_uart signal becomes high-power, it will enable the capture of the data store.
Figure 6-17. Storage Qualification equation
Step 4: Run the On-chip debugging feature
Step 4 Import a. cdc file. Run the on-chip debugging function to observe the debugging results.
 
1. Perform the following operation to generate a bus consisting of a 8-bit out_port signal.
 selects signals, from out_port<0> to out_port<7>.
 Right-click these signals, select Add to Busnew bus, and create the bus output_port.
Figure 6-18. Create a new Output_port bus
2. Set the data cache depth (depth): 16. (Fig. 6-19)
Figure 6-19 Selecting data Cache depth
3. Click the Apply Settings and Arm Trigger button. (Fig. 6-20)
Figure 6-20. Apply Settings and Arm Trigger
4. Enter "Xilinx #1 fpga!" at HyperTerminal to observe the information in Chipscope Analyzer. Right-click Out_portbus Radix, select the 馎 scii format. (Fig. 6-21)
 
Figure 6-21. Verify capture Results
Conclusion
Embedded ila nuclei and ICON cores into Picoblaze application design, set trigger conditions in Chipscope Analyzer, run on-chip debugging, and analyze waveforms in Chipscope-pro Analyzer.
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