新手求高手看下代码。好多错误。

这个是简易交通灯控制系统。脑快爆了
（1）        南北干道绿灯和东西干道的绿灯不能同时亮；如果同时亮，则应自动立即关闭信号灯系统，并立即发出报警信号（如LED灯）。
（2）        系统的初始状态是两个干道的红灯全亮。
（3）        系统工作后，首先东西干道红灯亮并维持20s，数码管的显示起始时间为19s，然后依次递减至0。前17s南北干道绿灯亮，后3s黄灯亮，期间数码管不显示。
（4）        然后，南北干道红灯亮并维持25s，数码管的显示起始时间为24s，然后依次递减至0。前20s东西干道绿灯亮，后5s黄灯亮，期间数码管不显示。
（5）        允许在紧急状态下，比如十字路口恶性交通事故时，两方向均为红灯，车辆禁止通行。当紧急状态解除后，重新计时并指示时间。
（6）        系统的南北干道和东西干道亮红灯的时间可由用户根据路况自设。比如在白天某一时段，南北干道的路段较繁忙，对应的通行时间较长。
（7）        如系统出现故障，不能正常显示，则黄灯全部闪烁以提醒车辆注意。

对 了。板子用的是MAS7000S 的EPM7128LS84-15
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JTD IS
        PORT(CLK:IN STD_LOGIC;
START,GZ,SG,RST:IN STD_LOGIC;
             RED:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--------4红灯         
                  YELLOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-----4黄灯           
GREEN:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -----4绿灯            
CNT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);------7端数码管的控制。        
DISPLAY:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-----7端数码管显示            
SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));      --片选
END JTD;
--------------------------------------------------------
ARCHITECTURE behave OF JTD IS
  SIGNAL COUNT:INTEGER RANGE 250 DOWNTO 0;
  SIGNAL A,LOAD,CLK1HZ:STD_LOGIC;
   SIGNAL DX,NB:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CNT1,CNT2,LOAD1,LOAD2:STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE states IS (guzhang,shigu,s0,s1,s2,s3);
SIGNAL current_state,next_state : states;
SIGNAL time_data:integer RANGE 0 TO 25;
BEGIN
--------------------------------------------------------
p1: PROCESS(CLK,CLK1HZ,COUNT)  --分频电路
    BEGIN
     IF CLK'EVENT AND CLK='1' THEN  
        COUNT<=0;
       IF COUNT<250 THEN
       COUNT<=COUNT+1;
     ELSE CLK1HZ<=NOT CLK1HZ;COUNT<=0;
     END IF;END IF;
     END PROCESS;
-------------------------------------------------------
p2: PROCESS(RST,GZ,START,CLK1HZ) --状态条件
    BEGIN
    IF CLK1HZ'EVENT AND CLK1HZ='1' THEN
      IF RST='1' THEN current_state<=shigu;
      ELSIF SG='1' THEN current_state<=shigu;
      ELSIF GZ='1' THEN current_state<=guzhang;
      ELSIF START='1' THEN current_state<=next_state;
      ELSE current_state<=current_state;
      END IF;
    END IF;
    END PROCESS;
------------------------------------------------------
p3: PROCESS(current_state,CLK1HZ,GZ,SG)--状态主进程
VARIABLE d0:STD_LOGIC_VECTOR(3 DOWNTO 0):="1111";   
VARIABLE d1:STD_LOGIC_VECTOR(3 DOWNTO 0):="1010";
VARIABLE d2:STD_LOGIC_VECTOR(3 DOWNTO 0):="0101";
VARIABLE d3:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
    BEGIN
    IF START='1' THEN
      IF RST='1' THEN
      CNT2<="0010"; CNT1<="0100";
      ELSIF CLK1HZ'EVENT AND CLK1HZ='1' THEN            
       IF LOAD='1' THEN CNT2<=LOAD2;CNT1<=LOAD1;  
        ELSIF CNT2="0000"AND CNT1="0000"THEN           
        CNT2<="0000";CNT1<="0000";
        ELSIF CNT1=9 THEN
           CNT1<="0000";
           IF CNT2=2 THEN
              CNT2<="0000";
           ELSE CNT2<=CNT2-1;
           END IF;
        ELSE  CNT1<=CNT1-1;
         END IF;
       END IF;
    ELSE CNT2<="0000";CNT1<="0000";      
    END IF;
    CASE current_state IS
    WHEN guzhang=> YELLOW<=CLK1HZ;
    WHEN shigu=>IF SG='1' OR START='0' THEN
                RED<=d0;YELLOW<=d3;GREEN<=d3;
                ELSE current_state<=s0;LOAD<='0';
    WHEN s0=>LOAD<='1';LOAD2<="0001";LOAD1<="1111";
             IF CNT2<2 THEN RED<=d1;GREEN<=d2;YELLOW<=d3;
             ELSIF CNT2=0 AND CNT1<3 THEN
             RED<=d1;GREEN<=d3;YELLOW<=d2;A<='0';
             ELSIF CNT2=0 AND CNT1=0 THEN
             current_state<=s1; A='1';
    WHEN s1=>LOAD<='1';LOAD2<="0010";LOAD1<="0100";
             IF CNT2<3 THEN RED<=d2;GREEN<=d1;YELLOW<=d3;
             ELSIF CNT2=0 AND CNT1<5 THEN
             RED<=d2;GREEN<=d3;YELLOW<=d1;A<='0';
             ELSIF CNT2=0 AND CNT1=0 THEN
             current_state<=shigu;A='1';
        END PROCESS;
-----------------------------------------------------
P4: PROCESS(CLK)      --显示电路
    VARIABLE Q:STD_LOGIC_VECTOR(2 DOWNTO 0);
    BEGIN
    IF CLK'EVENT AND CLK='1' THEN
       IF Q<1 THEN Q:=Q+1;
       ELSE Q:=(OTHERS=>'0');
       END IF;
    END IF;
    IF A='1' THEN
    IF Q="000" THEN CNT<=CNT1;
    ELSE IF Q="001" THEN CNT<=CNT2;
    END IF;END IF;
    ELSE CNT<="0000";
    END IF;
    SEL<=Q;
    CASE CNT IS
        WHEN "0000" => DISPLAY <="0111111";   --显示0
        WHEN "0001" => DISPLAY <="0000110";   --显示1
        WHEN "0010" => DISPLAY <="1011011";   --显示2
        WHEN "0011" => DISPLAY <="1001111";   --显示3
        WHEN "0100" => DISPLAY <="1100110";   --显示4
        WHEN "0101" => DISPLAY <="1101101";   --显示5
        WHEN "0110" => DISPLAY <="1111101";   --显示6
        WHEN "0111" => DISPLAY <="0000111";   --显示7
        WHEN "1000" => DISPLAY <="1111111";   --显示8
        WHEN "1001" => DISPLAY <="1101111";   --显示9
        WHEN "1010" => DISPLAY <="1000100";   --显示左转
        WHEN "1011" => DISPLAY <="1010000";   --显示右转
        WHEN OTHERS=>NULL;
        END CASE;
        END PROCESS;
END behave;

            编译结果。。。。看不懂。找不出
Info: Running Quartus II Analysis & Synthesis
        Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
        Info: Processing started: Sat Jun 04 22:46:28 2011
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off JTD -c JTD
Info: *******************************************************************
Error: VHDL error at JTD.vhd(73): type of identifier clk1hz does not agree with its usage as std_logic_vector type
Error: VHDL syntax error at JTD.vhd(77) near text "WHEN"; expecting "loop"
Error: VHDL syntax error at JTD.vhd(82) near text "="; expecting "'" or "(" or "."
Error: VHDL syntax error at JTD.vhd(88) near text "="; expecting "'" or "(" or "."
Error: VHDL syntax error at JTD.vhd(92) near text "VARIABLE"; expecting ":=" or "<="
Error: VHDL Type Conversion error at JTD.vhd(92): converted type of object near text or symbol std_logic_vector must match  void type of target object
Error: VHDL syntax error at JTD.vhd(93) near text "BEGIN"; expecting "end"
Error: VHDL Variable Assignment Statement error at JTD.vhd(95): target object q must be variable or aggregate
Error: VHDL Variable Assignment Statement error at JTD.vhd(96): target object q must be variable or aggregate
Error: VHDL expression error at JTD.vhd(95): illegal q in expression
Error: VHDL expression error at JTD.vhd(101): illegal q in expression
Error: VHDL expression error at JTD.vhd(100): illegal q in expression
Error: VHDL expression error at JTD.vhd(105): illegal q in expression
Error: VHDL error at JTD.vhd(105): type of identifier q does not agree with its usage as std_logic_vector type
Error: VHDL Interface Declaration error in JTD.vhd(106): interface object cnt of mode out cannot be read. Change object mode to buffer or inout.
Error: VHDL syntax error at JTD.vhd(121) near text "PROCESS"; expecting "if"
Error: VHDL error at JTD.vhd(122): type of identifier behave does not agree with its usage as  void type
Info: Found 0 design units, including 0 entities, in source file JTD.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 17 errors, 0 warnings
        Error: Processing ended: Sat Jun 04 22:46:29 2011
        Error: Elapsed time: 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 17 errors, 0 warnings