为了保证设计可靠性, 需要重点关注哪些方面？

为了保证设计可靠性, 需要重点关注哪些方面？  
答：Here are a few guidelines for reliable FPGA design（关于可靠性FPGA设计的几点建议）
①        Use fully synchronous design.  Asynchronous design is very sensitive to path delay and is therefore not robust.  An example of asychronous circuit is the SR latch which uses combinational feedback. （使用完全同步设计. 异步设计对路径延迟非常敏感, 因此不很可靠. 异步电路的一个例子是使用组合反馈的SR闭锁. ）
②        Never gate your clock signal with combinational logic.  Glitches may occur on any gated clock signals,  which results in false triggering of flip-flops. （绝不使用组合逻辑控制时钟信号. 因为在任何门控制时钟信号上可能产生短时脉冲干扰, 最终导致错误触发flip-flop. ）
③        Never rely on gate delay. （绝不要依靠门延迟. ）
④        Enough bypass capacitors should be placed close to the power and ground pins of FPGA.  Use capacitors with good high frequency response. （FPGA的电源和接地引脚附近应该放置足够多的旁路电容器. 使用优质高频响应电容器. ）
⑤        Always use the global clock buffers on the FPGA to drive internal clock signals.  These clock buffers and the associated clock distribution network have been carefully designed to minimize skew. （在FPGA上始终使用全局时钟缓冲来驱动内部时钟信号. 并且已经仔细设计了这些时钟缓冲和关联时钟配电网, 以将畸变减至最小. ）