经常看到gate这个词. 能够具体解释一下它的含义, 例举其用法以及如何避免问题？

经常看到gate这个词. 能够具体解释一下它的含义, 例举其用法以及如何避免问题？
答：Here're a couple of examples :（举例说明）
- Never use gated clock.  By gated clock we mean the clock signal comes out from combinational logic.  It is well known that any signal coming out of combinational logic is prone to glitch.  The result is fatal if there is a glitch on your clock signal since it will cause false triggering of FFs.  A common technique to avoid gated clock is to utilize the clock enable pin on the FF. （从不使用gated clock. 这个词表示时钟信号出自组合逻辑. 众所周知, 任何出自组合逻辑的信号都容易发生故障. 由于时钟信号上的故障将导致错误触发FF, 其结果是致命的. 避免gated clock常用的技巧是利用FF上的时钟使能引脚. ）
-        Never design a circuit that relies on gate delay to function.  It was a common practise in the past to introduce a delay in the design by inserting a series of logic gates.  This is not a recommended style in modern high speed digital design since the delay changes as new devices coming out from more advance process technologies.  Also,  the amount of delay changes as temperature and voltage as well.  So it is not a good design practice to have circuits which relies in gate delay to function.  （绝不设计依赖gate delay工作的电路. 通过插入一系列逻辑门在设计中引入延迟, 这是以前常见的作法. 而在现代高速数字设计中, 建议不要使用这种作法, 因为延迟会随采用更先进的工艺技术所制造的新器件而改变. 而且, 延迟的总量也会随温度和电压而改变. 因此依赖gate delay而工作的电路不是很好的设计. ）