verilog模块

模块结构
    端口： module 模块名(端口1, 端口2, 端口3)
    内容：
        I/O说明：
            input 端口名;
            output 端口名;
        内部信号：
            reg [width-1:0]  r变量1,r变量2;
            wire [width-1:0] w变量1,w变量2;
        功能定义：
            a. assign 连线
                assign a = b&c;
            b. 实例化其他元件
                and and_inst(q, a, b);
            c. always模块
                always @(posedge clk or posedge clr)
                begin
                    if(clr) 
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= 0;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; else
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if(en)
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <= d;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; end