m序列verilog

module pn_7(clk, clr_n, pn_out);
input clk; //时钟输入
input clr_n; //复位输入
output pn_out; //pn码输出
reg [6:0]register; //7位移位寄存器
parameter sta_start = 7'B1000000; //初试状态，可自己定
assign pn_out = register[1];
always @(posedge clk)
begin
if (!clr_n) register <= sta_start;
else register <= {register[0]+register[4],register[6:1]};
end
endmodule

m序列verilog

m序列verilog