verilog测试模板

a=",a);
  reg [31:0] b = 4'd5;
  initial $displayb("b=",b);
  reg [31:0] c = 4'h5b_3;
  initial $displayb("c=",c);
  reg [31:0] d = -8'b101;
  initial $displayb("d=",d);
  reg [31:0] e= 10'o752;
  initial $displayb("e=",e);
  reg [31:0] f = 8'hf;
  initial $displayb("f=",f);
  reg [31:0] g = 12'hxa;
  initial $displayb("g=",g);
  reg [31:0] h = -8'sha9;
  initial $displayb("h=",h);
  reg [31:0] i = 8'ha9;
  initial $displayb("i=",i);
  reg [31:0] j = -4'sha;
  initial  $displayb("j=",j);
endmodule

verilog测试模板