为什么我的输出都接地啦？？？？？？？？？？？？？？

为什么我的输出都接地啦？？？？？？？？？？？？？？
module hx711(clk,reset,out_reg,ADDO,ADSK);
input clk,reset;
inout reg ADDO=1,ADSK;
output   [23:0] out_reg;
reg [23:0] out_reg;
reg [4:0] count;
reg [1:0] case_3;
reg [2:0] case_2,case_1;
reg [1:0] t;
reg mclk;
always @(posedge clk or negedge reset) begin
if(!reset) begin
end
else begin
case(case_3)
0:begin
    ADDO<=1'b1;
    ADSK<=1'b0;
    out_reg<=24'd0;
    case_3<=2'd1;
end
1:begin
if(ADDO==1'd0)
case_3<=2'd2;
end
2:begin
cnt_1us_clear <= 0;
case_3<=2'd3;
end
3:begin
    if(cnt_1us >= 10)
  if(count>=5'd24) begin
case(case_1)
0:begin
cnt_1us_clear <= 0;
ADSK<=1;
case_1<=3'd1;
end
1:begin
if(cnt_1us >= 20) begin
ADSK<=0;
cnt_1us_clear <= 1;
case_1<=3'd2;
end
else
cnt_1us_clear <= 0;
end
2:begin
cnt_1us_clear <= 0;
case_1<=3'd3;
end
3:begin
if(cnt_1us >= 20) begin
if(t==2'd0) begin
cnt_1us_clear <= 1;
case_1<=3'd3;
t<=0;
end
else begin
case_1<=3'd0;
cnt_1us_clear <= 1;
t=t+2'd1;
end
end
end
4:begin
ADSK<=1;
case_1<=3'd4;
cnt_1us_clear <= 0;
end
5:begin
if(cnt_1us >= 100) begin
case_1<=3'd5;
cnt_1us_clear <= 1;
end
end
6:begin
//out<=out_reg;
count<=5'd0;
case_1<=2'd0;
case_3<=2'd0;
case_2<=2'd0;
end
endcase
  end
  else begin
case(case_2)
0:begin
   cnt_1us_clear <= 1;
   case_2<=3'd1;
  end
1:begin
ADSK<=1'b1;
case_2<=3'd2;
cnt_1us_clear <= 0;  
  end
2:begin
if(cnt_1us >= 20) begin
out_reg<={out_reg[22:0],out_reg[23]};
case_2<=3'd3;
cnt_1us_clear <= 1;
end
else
cnt_1us_clear <= 0;
  end
3:begin
cnt_1us_clear <= 0;
ADSK<=1'd0;
case_2<=3'd4;
  end
4:begin
if(cnt_1us >= 20) begin
      if(ADDO)
out_reg<=out_reg+24'd1;
    count<=count+1'b1;
    case_2<=3'd0;
    cnt_1us_clear <= 1;     
end
else
cnt_1us_clear <= 0;
  end
endcase
   end
end
endcase
end
end




//assign out=out_reg;

reg [19:0] cnt_1us;                      // 1us延时计数子
reg cnt_1us_clear;                       // 请1us延时计数子
reg [5:0] cnt;                         // 计数子
always @ (posedge clk or negedge reset)
  if (!reset)
    cnt <= 0;
  else
    if (cnt == 49)
      cnt <= 0;
    else
      cnt <= cnt + 1'b1;

reg clk_1us;                            // 1MHz 时钟

always @ (posedge clk or negedge reset)
  if (!reset)
    clk_1us <= 0;
  else
    if (cnt <= 24)                      // 24 = 50/2 - 1
      clk_1us <= 0;
    else
      clk_1us <= 1;      

always @ (posedge clk_1us)
  if (cnt_1us_clear)
    cnt_1us <= 0;
  else
    cnt_1us <= cnt_1us + 1'b1;
endmodule
out_reg编译时总是接地啊
编译后，只占了3个LE啊

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