888| 0
|
请教个问题,我这边在outputlogic生成的crc检验模块,这边有posedge rst,加上这个c... |
|小黑屋|手机版|Archiver|fpga论坛|fpga设计论坛
( 京ICP备20003123号-1 )
GMT+8, 2025-6-8 05:12 , Processed in 0.059685 second(s), 20 queries .
Powered by Discuz! X3.4
© 2001-2023 Discuz! Team.