我写的IIR 滤波器程序，输入正弦波，出来却是方波，求高手帮忙查找一下问题！谢了！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity IIR is
port(clk,reset:in std_logic;
         data_in:in std_logic_vector(9 downto 0);
         data_outut std_logic_vector(11 downto 0));
end entity;

architecture beh of IIR is
signal data_out_x: std_logic_vector(11 downto 0);
signal x0,x1,x2,y0,y1,y2:std_logic_vector(10 downto 0);
signal x0_result,x1_result,x2_result,y0_result,y1_result,y2_result:std_logic_vector(24 downto 0);
signal foward_feedback,afterward_feedback:std_logic_vector(24 downto 0);
signal data:std_logic_vector(24 downto 0);

constant a1:std_logic_vector(13 downto 0):=conv_std_logic_vector(-7644,14);
constant a2:std_logic_vector(13 downto 0):=conv_std_logic_vector(3549,14);
constant b0:std_logic_vector(13 downto 0):=conv_std_logic_vector(273,14);
--constant b1:std_logic_vector(12 downto 0):=conv_std_logic_vector(0,14);
constant b2:std_logic_vector(13 downto 0):=conv_std_logic_vector(-273,14);

component lpm_mult0 IS
        PORT
        (
                dataa                : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
                datab                : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
               
                result                : OUT STD_LOGIC_VECTOR (24 DOWNTO 0)
        );
END component;

begin
process(reset,clk)
begin
if rising_edge(clk)then
        if(reset='0')then
        x0<=(others=>'0');
        x1<=(others=>'0');
        x2<=(others=>'0');
    else
        x0<=data_in(9)&data_in;
        x1<=x0;
        x2<=x1;
        end if;
end if;
end process;
u1:lpm_mult0 port map(b0,x0,x0_result);
--u2:lpm_mult0 port map (b1,x1,x1_result);
u3:lpm_mult0 port map (b2,x2,x2_result);
foward_feedback<=x0_result+x2_result;--x1_result+

process(reset,clk)
begin
if rising_edge(clk)then
        if(reset='0')then
        y0<=(others=>'0');
        y1<=(others=>'0');
        y2<=(others=>'0');
    else
        y0<=data(24 downto 14);
        y1<=y0;
        y2<=y1;
        end if;
end if;
end process;

u5:lpm_mult0 port map (a1,y1,y1_result);
u6:lpm_mult0 port map (a2,y2,y2_result);
afterward_feedback<=y2_result+y1_result;--+y0_result;

data<=foward_feedback+afterward_feedback;

process(clk,reset)
begin
if rising_edge(clk)then
        if reset='0' then
        data_out_x<=(others=>'0');
        else
        data_out_x<=data(24 downto 13);
        end if;
end if;
end process;

data_out<=data_out_x;
end;

自己顶一下，急求高手帮忙！

为什么就没有哪位大侠帮一下啊！

建议你根据仿真模型图，认真的梳理一下程序，另外和你的测试文件可能也有关系的！！！！！！！