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 本帖最后由 xiasitai 于 2011-10-10 22:43 编辑  
 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity time4 is 
port(a:in std_logic; 
     b:in std_logic; 
          clk:in std_logic; 
          pp: out std_logic; 
          np: out std_logic); 
end time4; 
 
architecture Behavioral of time4 is 
signal prestate,state: std_logic_vector(1 downto 0); 
signal snp,spp:std_logic; 
begin 
process(a,b,clk) 
begin 
if(clk'event and clk='1')then 
state<=a&b; 
if state="00" then 
case prestate is 
when "01"=>prestate<="00";spp<='1'; 
when "10"=>prestate<="00";snp<='1'; 
when others=>prestate<="00";spp<='0';snp<='0'; 
end case; 
elsif state="10" then 
case prestate is 
when "00"=>prestate<="10";spp<='1'; 
when "11"=>prestate<="10";snp<='1'; 
when others=>prestate<="10";spp<='0';snp<='0'; 
end case; 
elsif state="11" then 
case prestate is 
when "10"=>prestate<="11";spp<='1'; 
when "01"=>prestate<="11";snp<='1'; 
when others=>prestate<="11";spp<='0';snp<='0'; 
end case; 
else  
case prestate is 
when "11"=>prestate<="01";spp<='1'; 
when "00"=>prestate<="01";snp<='1'; 
when others=>prestate<="01";spp<='0';snp<='0'; 
end case; 
end if; 
end if; 
end process; 
pp<=spp; 
np<=snp; 
end Behavioral; |   
 
 
 
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