求高手帮助 谢谢

`include "muxtwo.v"
module t;
reg ain,bin,select;
reg clock;
wire outw;
initial
begin
ain=0;
bin=0;
select=0;
clock=0;
end
always #50 clock=~clock;
always @(posedge clock)
begin
#1 ain={$ random%}2;
#3 bin={$ random}%2;
end
always # 10000 select=!select;
muxtwo m(.out(outw),.a(ain),.b(bin),.sl(select));
endmodule
Error (10170): Verilog HDL syntax error at t.v(16) near text $
Error (10170): Verilog HDL syntax error at t.v(16) near text "$";  expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator
Error (10170): Verilog HDL syntax error at t.v(17) near text $
Error (10170): Verilog HDL syntax error at t.v(17) near text "$";  expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator
Error (10112): Ignored design unit "t" at t.v(2) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 3 warnings
        Error: Peak virtual memory: 182 megabytes
        Error: Processing ended: Tue Oct 25 10:53:12 2011
        Error: Elapsed time: 00:00:06
        Error: Total CPU time (on all processors): 00:00:03错误在哪啊？

行为模块是不可综合的，你这个是测试模块，$与random之间没有空格，多看看书，把基本的弄明白