请 高手编个电子钟程序,要带按键的,看看我的程序怎么去抖动

1. module clk(Clk0,Clk1,Change,Mkey,Hkey,SEG,DIG);
   
2. input        Clk0,Clk1,Change,Mkey,Hkey;//clk0为FPGA晶振频率，clk1为1hz时钟频率
   
3. output [7:0] SEG,DIG;//数码管的段选和位选
   
4. reg [12:0]   CNT_R0;
   
5. reg          F_OUT;
   
6. reg [7:0]    HOUR,MIN,SEC;
   
7. wire         hclk,mclk;
   
8. reg          flag,mc,hc;
   
9. reg [2:0]    SCAN_R;
   
10. reg [3:0]    SEG_M [7:0];
    
11. reg [7:0]    SEG_DR;
    
12. reg [7:0]    SEG,DIG;
    
13. always @(posedge Clk0)//分频
    
14. begin
    
15.    CNT_R0 <= CNT_R0 + 1'b1;
    
16.   
    
17.    if(CNT_R0 < 4096)
    
18.    begin
    
19.       F_OUT <= 1;
    
20.    end
    
21.    else
    
22.    begin
    
23.       F_OUT <= 0;
    
24.    end
    
25. end
    
26. always @(posedge F_OUT)
    
27. begin
    
28.    SCAN_R = SCAN_R + 1'b1;
    
29.   
    
30.    case(SCAN_R)
    
31.       3'h0 : begin DIG = 8'hFE  ; SEG_DR = SEG_M[0]; end
    
32.       3'h1 : begin DIG = 8'hFD  ; SEG_DR = SEG_M[1]; end
    
33.       3'h2 : begin DIG = 8'hFB  ; SEG_DR = SEG_M[2]; end
    
34.       3'h3 : begin DIG = 8'hF7  ; SEG_DR = SEG_M[3]; end
    
35.       3'h4 : begin DIG = 8'hEF  ; SEG_DR = SEG_M[4]; end
    
36.       3'h5 : begin DIG = 8'hDF  ; SEG_DR = SEG_M[5]; end
    
37.       3'h6 : begin DIG = 8'hBF  ; SEG_DR = SEG_M[6]; end
    
38.       3'h7 : begin DIG = 8'h7F  ; SEG_DR = SEG_M[7]; end
    
39.    endcase
    
40. end
    
41. always @(posedge Clk0)
    
42. begin
    
43.    case(SEG_DR)
    
44.       4'h0 : SEG <= 8'h3F;
    
45.       4'h1 : SEG <= 8'h06;
    
46.       4'h2 : SEG <= 8'h5B;
    
47.       4'h3 : SEG <= 8'h4F;
    
48.       4'h4 : SEG <= 8'h66;
    
49.       4'h5 : SEG <= 8'h6D;
    
50.       4'h6 : SEG <= 8'h7D;
    
51.       4'h7 : SEG <= 8'h07;
    
52.       4'h8 : SEG <= 8'h7F;
    
53.       4'h9 : SEG <= 8'h6F;
    
54.       4'hA : SEG <= 8'h40;
    
55.    default : SEG <= 4'h00;  
    
56.    endcase
    
57. end
    
58. always @(posedge Change)//选择手动调时还是正常计时
    
59. begin
    
60. if(flag==0)
    
61. flag<=1;
    
62. else
    
63. flag<=0;
    
64. end
    
65. always @(posedge Clk1)
    
66. begin
    
67.    if(SEC==8'b01011001)begin SEC<=0; if(flag==0)mc<=1;else mc<=mc;end
    
68.    else begin
    
69.    if(SEC[3:0]==4'b1001)
    
70.    begin SEC[3:0]<=0;SEC[7:4]<=SEC[7:4]+1'b1;if(flag==0)mc<=0;else mc<=mc;end
    
71.    else
    
72.    begin
    
73.        SEC[3:0]<=SEC[3:0]+1'b1;if(flag==0)mc<=0;else mc<=mc; end
    
74.    end  
    
75. end
    
76. assign mclk=(flag==0)?(!flag&mc):(!mc&Mkey)|(mc&!Mkey);
    
77. always @(posedge mclk)
    
78. begin
    
79.    if(MIN==8'b01011001)begin MIN<=0; if(flag==0)hc<=1;else hc<=hc;end
    
80.    else begin
    
81.    if(MIN[3:0]==4'b1001)
    
82.    begin
    
83. MIN[3:0]<=0;MIN[7:4]<=MIN[7:4]+1'b1;if(flag==0)hc<=0;else hc<=hc;end
    
84.    else
    
85.    begin
    
86.        MIN[3:0]<=MIN[3:0]+1'b1;if(flag==0)hc<=0;else hc<=hc; end
    
87.    end  
    
88. end
    
89. assign hclk=(flag==0)?(!flag&hc):(!hc&Hkey)|(hc&!Hkey);
    
90. always @(posedge hclk)
    
91. begin
    
92.    if(HOUR==8'h00100011) HOUR<=0;
    
93.    else  begin
    
94. if(HOUR[3:0]==4'b1001)begin HOUR[3:0]<=0;HOUR[7:4]<=HOUR[7:4]+1'b1;end
    
95. else
    
96.        HOUR[3:0]<=HOUR[3:0]+1'b1;  
    
97. end
    
98. end
    
99. always @(posedge Clk0)
    
100. begin
     
101.    SEG_M[0] = SEC[3:0];
     
102.    SEG_M[1] = SEC[7:4];
     
103.    SEG_M[2] = 4'hA;  
     
104.    SEG_M[3] = MIN[3:0];
     
105.    SEG_M[4] = MIN[7:4];
     
106.    SEG_M[5] = 4'hA;
     
107.    SEG_M[6] = HOUR[3:0];
     
108.    SEG_M[7] = HOUR[7:4];
     
109. end
     
110. endmodule
     

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