公司目前招聘2名高级FPGA工程师,如您觉得符合我司该岗位要求,可毛遂自荐将您的个人简历和作品邮件给我,我会在收到简历后尽快与您取得联系。(薪酬面议,工作地点在上海徐汇区漕河泾这)
邮箱:yuting.li@saicocch.com
Senior FPGA Engineer
Responsibilities
As a Senior FPGA Engineer, you will be responsible for specification, FPGA logic design, simulation, synthesis, timing analysis, integration and lab debug. You will participate in verification, board design, diagnostics and/or firmware integration. The job also entails mentoring junior engineers and extending your engineering capacity through them.
Requirements
§ Bachelor/Master’s degree in Electrical Engineering
§ At least 5 years of direct FPGA design experience
§ Solid understanding of FPGA tools
§ Experience developing FPGA RTL code and simulation test benches using VHDL/Verilog.
§ Experience developing simulation test benches § Experience with code-coverage tools
§ Design experience with multi-gigabit serial I/O a MUST
§ Experience with one or more scripting languages for FPGA design/verification process automation
§ Experience with command-line automation of FPGA design/synthesis/verification process
§ Ability to debug complex architectural designs on simulation and in real hardware.
§ Ability to read PCB schematics and device datasheets for design review and debug
§ Ability to read PCB layout data files to probe and debug FPGA interfaces
§ Strong laboratory experience using scopes and logic analyzers
§ Candidates with fibre channel or networking product design experience a strong plus
§ Good English reading skills required
高级FPGA工程师
工作职责:
负责相关规格的制定,FPGA逻辑的设计,能进行代码的仿真,综合,时序分析和实验室调试。将参与产品的验证,板级设计,调试以及软件的整合。作为高级工程师,能带领下面的工程师开展工作和共同进步。
职位要求:
1. 电子信息类本科/硕士学位毕业
2. 良好的工作态度和团队协作意识,认真负责,自我激励
3. 至少5年FPGA设计经验
4. 熟练使用FPGA设计相关工具
5. 有 FPGA RTL code 经验和 VHDL/Verilog test bench的编写经验
6. 大型项目的test bench 的编写经验
7. 有使用code-coverage 工具的相关经验
8. 必须有过千兆串行接口的设计经验
9. 掌握一种以上的FPGA设计/验证的自动脚本语言
10. 复杂系统的设计,调试,仿真能力,包括代码级和实际硬件。
11. 能看懂线路图和PCB,相关元件的datasheet,并参与检查和调试
12. 能看懂PCB文档,对FPGA的相关引脚进行实际信号的测试
13. 能熟练使用示波器和逻辑分析仪
14. 光通讯和网络产品的相关设计经验优先
15. 良好的英语阅读能力 |