交织程序不懂，求指导

-- ================================================================
-- File: Interleaver.vhd
-- Version: v1.1
-- Author: olivercamel
-- Date: 4.16.2006
-- Description:
-- This vhdl programme is to generate a Interleaver which works together with R-S
-- encoder/decoder to mitigate the effects of noise in communications system.
-- Actually, interleaver is a simple RAM controller that writes datas into or reads
-- datas outside following specific orders. For example, symbols we used in this
-- project are comprised by 6 words. Throughput of the interleaver is 6 symbols.
-- And then, the input sequence is s1w1,s1w2,s1w3,s1w4,s1w5,s1w6,s2w1,s2w2,...,
-- s6w5,s6w6. The output sequence is s1w1,s2w1,s3w1,s4w1,s5w1,s6w1,s1w2,s2w2,...,
-- s5w6,w6w6. A 4bit * 64words RAM named ram_Interleaver is required in the codes.
-- Revision History:
-- v1.1, 4.27.2006, deassert sink_ena earlier to avoid a control bug.
-- ================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- ================================================================
entity Interleaver is
port
(
                                          -- clock input
  clk: in std_logic;
                                            -- asynchroism clear input
  aclr: in std_logic;
                                            -- 4bit width Data ports
    inputData: in std_logic_vector (3 downto 0);
    outputData: out std_logic_vector (3 downto 0);
                                            -- simple ALTERA Atlantic interface ports
  sink_val: in std_logic;
  sink_sop: in std_logic;
  sink_eop: in std_logic;
  sink_ena: out std_logic;
  source_val: out std_logic;
  source_sop: out std_logic;
  source_eop: out std_logic;
  source_ena: in std_logic
);
end Interleaver;  
-- ================================================================

architecture structure of Interleaver is
-- --------------------------------------------------------------------------------
-- component declaration
-- generate by ALTERA ip toolbench
-- name: ram_Interleaver
-- size: 4bit * 64words
component ram_Interleaver
PORT
(
  aclr: IN STD_LOGIC;
  clock: IN STD_LOGIC;
  data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
  rdaddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
  rden: IN STD_LOGIC;
  wraddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
  wren: IN STD_LOGIC;
  q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component;

-- signals those connect to RAM
signal clk_ram: std_logic;
signal aclr_ram: std_logic;
signal inputData_ram: std_logic_vector (3 downto 0);
signal outputData_ram: std_logic_vector (3 downto 0);
signal readEnable_ram: std_logic;
signal writeEnable_ram: std_logic;
signal readAddress_ram: std_logic_vector (5 downto 0);
signal writeAddress_ram: std_logic_vector (5 downto 0);

-- signals those used to Atlantic interface outputs
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;
signal interval_sink_ena: std_logic;

-- flag signal indicates status: '1' input process, '0' output process`   
signal inoutFlag: std_logic;

-- write address
signal wrAddNum: integer range 0 to 36;
-- read address
signal rdAddNum: integer range 0 to 36;
-- write enable
signal writeEnable: std_logic;
-- read enable
signal readEnable: std_logic;

-- delayd signals

-- sink_eop delay
signal sink_eop_d: std_logic;
-- readEnable delay
signal readEnable_d0: std_logic;
signal readEnable_d1: std_logic;
-- interval_source sop and eop delay or acceleration
signal interval_source_sop_d0: std_logic;
signal interval_source_sop_d1: std_logic;
signal interval_source_eop_a: std_logic;
signal interval_source_eop_d0: std_logic;
signal interval_source_eop_d1: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- part1: ram connections
-- ram ports map
u1: ram_Interleaver port map
(
    clock => clk_ram, aclr => aclr_ram,
    data => inputData_ram, q => outputData_ram,
  rdaddress => readAddress_ram, wraddress => writeAddress_ram,
  rden => readEnable_ram, wren => writeEnable_ram
);

-- integer converts to std_logic_vector
readAddress_ram <= conv_std_logic_vector(rdAddNum,6);
writeAddress_ram <= conv_std_logic_vector(wrAddNum,6);

-- readEnable delay
process(clk,readEnable)
begin
  if falling_edge(clk) then
  readEnable_d0 <= readEnable;
  readEnable_d1 <= readEnable_d0;
end if;
end process;

writeEnable_ram <= writeEnable;
readEnable_ram <= readEnable_d0;

clk_ram <= clk;
aclr_ram <= aclr;

inputData_ram <= inputData;

-- outputs data at clk's falling edge
process(aclr,clk,outputData_ram)
begin
  if aclr = '1' then
  outputData <= "0000";
else
  if falling_edge(clk) then          -- using falling edge
   outputData <= outputData_ram;
  end if;
end if;
end process;
-- --------------------------------------------------------------------------------

-- part2: generate Flag signal inoutFlag

-- delay input signal sink_eop
process(clk,sink_eop)
begin
  if rising_edge(clk) then
  sink_eop_d <= sink_eop;
end if;
end process;

-- control inoutFlag
process(clk,aclr,sink_eop_d,interval_source_eop_a)
begin
  if aclr = '1' then
  inoutFlag <= '1';
else
  if rising_edge(clk) then
      if inoutFlag = '1' then
    if sink_eop_d = '1' then
     inoutFlag <= '0';
    end if;
   else
    if interval_source_eop_a = '1' then
     inoutFlag <= '1';
    end if;
   end if;
  end if;
end if;
end process;

-- --------------------------------------------------------------------------------

-- part3: generate read/write Enable/Address

-- generate writeEnable
process(aclr,inoutFlag,sink_val)
begin
  if aclr = '1' then
  writeEnable <= '0';
else
    if inoutFlag = '1' then
   writeEnable <= sink_val;
  else
   writeEnable <= '0';
  end if;
end if;
end process;

-- generate readEnable
process(clk,aclr,inoutFlag,source_ena)
begin
  if aclr = '1' then
  readEnable <= '0';
else
  if falling_edge(clk) then -- using falling edge
      if (inoutFlag = '0') and (source_ena = '1') then
    readEnable <= '1';
   else
    readEnable <= '0';
   end if;
  end if;
end if;
end process;

-- write address
process(clk,aclr,writeEnable,sink_sop,sink_eop)
begin
  if  aclr = '1' then
  wrAddNum <= 1;
else
  if falling_edge(clk) then -- using falling edge
      if writeEnable = '1' then
    if wrAddNum = 36 then
     wrAddNum <= 1;
    else
     wrAddNum <= wrAddNum + 1;
    end if;
   end if;
      if sink_sop = '1' then
    wrAddNum <= 2;
      elsif sink_eop = '1' then
    wrAddNum <= 1;
   end if;
  end if;
end if;
end process;

-- read address
process(clk,aclr,source_ena,interval_sink_ena)
begin
  if aclr = '1' then
  rdAddNum <= 0;
else
  if falling_edge(clk) then -- using falling edge
    if readEnable = '1' then
            if rdAddNum = 0 then
                     rdAddNum <= 1;
            elsif rdAddNum = 31 then
                     rdAddNum <= 2;
            elsif rdAddNum = 32 then
                     rdAddNum <= 3;
            elsif rdAddNum = 33 then
                     rdAddNum <= 4;
            elsif rdAddNum = 34 then
                     rdAddNum <= 5;
            elsif rdAddNum = 35 then
                     rdAddNum <= 6;
            else
                     rdAddNum <= rdAddNum + 6;
            end if;
          end if;
    if rdAddNum = 36 then
            rdAddNum <= 0;
           end if;
  end if;
end if;
end process;

-- --------------------------------------------------------------------------------
-- part4: Atlantic interface signals


-- source sop eop is controlled by rdAddNum
-- generate interval_source_eop_a at the same time
process(rdAddNum)
begin
  case rdAddNum is
  when 36 =>
   interval_source_eop <= '1';
   interval_source_sop <= '0';
   interval_source_eop_a <= '0';
  when 1 =>
   interval_source_sop <= '1';
   interval_source_eop <= '0';
   interval_source_eop_a <= '0';
  when 30 =>
   interval_source_sop <= '0';
   interval_source_eop <= '0';
   interval_source_eop_a <= '1';
  when others =>
   interval_source_sop <= '0';
   interval_source_eop <= '0';
   interval_source_eop_a <= '0';
end case;
end process;

-- source_sop source_eop delay and output
process(clk,interval_source_sop)
begin
  if rising_edge(clk) then
  interval_source_sop_d0 <= interval_source_sop;
  interval_source_sop_d1 <= interval_source_sop_d0;
end if;
end process;

process(clk,interval_source_eop)
begin
  if rising_edge(clk) then
  interval_source_eop_d0 <= interval_source_eop;
  interval_source_eop_d1 <= interval_source_eop_d0;
end if;
end process;



process(clk,interval_source_sop_d1,interval_source_eop_d1)
begin
  if falling_edge(clk) then -- using falling edge
  source_sop <= interval_source_sop_d1;
  source_eop <= interval_source_eop_d1;
end if;
end process;

-- generate sink_ena
process(clk,aclr,wrAddNum,rdAddNum)
begin
  if aclr = '1' then
  interval_sink_ena <= '1';
else
  if rising_edge(clk) then
      if wrAddNum = 35 then                  -- edited in v1.1 deassert sink_ena earlier
    interval_sink_ena <= '0';
      elsif rdAddNum = 36 then
    interval_sink_ena <= '1';
   end if;
  end if;
end if;
end process;

sink_ena <= interval_sink_ena;

-- generate source_val
process(clk,readEnable_d1)
begin
  if falling_edge(clk) then -- using falling edge
  interval_source_val <= readEnable_d1;
end if;
end process;

source_val <= interval_source_val;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================
-- File: interleaver1.vhd
-- DATE: 2008-3-30
-- Mode: QAM-16
-- Description:
-- This vhdl programme is to generate a Interleaver which works together with R-S
-- encoder/decoder to mitigate the effects of noise in communications system.
-- Actually, interleaver is a simple RAM controller that writes datas into or reads
-- datas outside following specific orders.
--======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--======================================================================
entity Interleaver1 is
        port
        (
                               -- clock input
                clk: in std_logic;
                               -- asynchroism clear input
                aclr: in std_logic;
                               -- 4bit width Data ports
                inputData: in std_logic;
                outputData: out std_logic;
                               -- simple ALTERA Atlantic interface ports
                sink_val: in std_logic;
                sink_sop: in std_logic;
                sink_eop: in std_logic;
                sink_ena: out std_logic;
                source_val: out std_logic;
                source_sop: out std_logic;
                source_eop: out std_logic;
                source_ena: in std_logic
        );
end Interleaver1;
--======================================================================
architecture structure of Interleaver1 is
-- --------------------------------------------------------------------------------
-- signals those used to Atlantic interface outputs
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;
signal interval_sink_ena: std_logic;

-- flag signal indicates status: '1' input process, '0' output process`       
signal inoutFlag: std_logic;

-- interleaver ram
signal interleaver_ram: std_logic_vector(1536 downto 0);

-- write address
signal wrAddNum,internal_wrAddNum: integer range 0 to 1536;
--signal writeAddress: std_logic_vector(3 downto 0);

-- read address
signal rdAddNum,internal_rdAddNum: integer range 0 to 1536;
--signal readAddress: std_logic_vector(3 downto 0);

-- write enable
signal writeEnable: std_logic;

-- read enable
signal readEnable: std_logic;

-- delayed signals

-- sink_eop delay
signal sink_eop_d: std_logic;

-- readEnable delay
signal readEnable_d0: std_logic;
signal readEnable_d1: std_logic;

-- interval_source sop and eop delay or acceleration
signal interval_source_sop_d0: std_logic;
signal interval_source_sop_d1: std_logic;
signal interval_source_eop_a: std_logic;
signal interval_source_eop_d0: std_logic;
signal interval_source_eop_d1: std_logic;

signal flag1,flag2: std_logic;
signal flag1_d0,flag2_d0: std_logic;
-- --------------------------------------------------------------------------------
begin
-- --------------------------------------------------------------------------------
-- part1: ram connections

-- integer converts to std_logic_vector
sink_ena<='1';

-- readEnable delay
process(clk,readEnable)
begin
        if falling_edge(clk) then
                readEnable_d0 <= readEnable;
        end if;
        if rising_edge(clk) then
                readEnable_d1 <= readEnable;
        end if;
end process;

-- inputs data at clk's rising edge
process(aclr,clk,writeEnable)
begin
        if aclr = '1' then
                interleaver_ram <= (others=>'0');
        else
                if rising_edge(clk) then     -- using rising edge
                   if writeEnable='1' then
                          interleaver_ram(wrAddNum) <= inputData;
                   end if;         
                end if;
        end if;
end process;

-- outputs data at clk's falling edge
process(aclr,clk,readEnable_d1)
begin
        if aclr = '1' then
                outputData <= 'Z';
        else
            if falling_edge(clk) then -- using falling edge
                   if readEnable_d1='1' then
                           outputData <= interleaver_ram(rdAddNum);
                   else
                       outputData <='Z';
                   end if;         
                end if;       
        end if;
end process;

-- --------------------------------------------------------------------------------
-- part2: generate Flag signal inoutFlag

--Flag1
process(clk,aclr,wrAddNum,internal_rdAddNum)
begin
        if aclr = '1' then
                flag1 <= '0';
        elsif falling_edge(clk) then
                        if internal_wrAddNum = 768 then
                                flag1 <= '1';
                        elsif rdAddNum = 768 then
                                        flag1 <= '0';
                        end if;
        end if;
end process;

--Flag2
process(clk,aclr,wrAddNum,internal_rdAddNum)
begin
        if aclr = '1' then
                flag2 <= '0';
        elsif falling_edge(clk) then
                        if internal_wrAddNum = 1536 then
                                flag2 <= '1';
                        elsif rdAddNum = 1536 then
                                        flag2 <= '0';
                        end if;
        end if;
end process;

--Flag1 delay
process(clk,aclr,flag2,flag1)
begin
        if rising_edge(clk) then
                       
                flag1_d0 <= flag1;
                flag2_d0 <= flag2;

        end if;
end process;
-- --------------------------------------------------------------------------------
-- part3: generate read/write Enable/Address

-- generate writeEnable
process(aclr,inoutFlag,sink_val)
begin
        if aclr = '1' then
                writeEnable <= '0';
        else
                --if inoutFlag = '1' then
                        writeEnable <= sink_val;
                --else
                --        writeEnable <= '0';
                --end if;
        end if;

end process;

-- generate readEnable
process(clk,aclr,inoutFlag,source_ena)
begin
        if aclr = '1' then
                readEnable <= '0';
        else
                if rising_edge(clk) then -- using falling edge
                        if source_ena = '1' then
                            if wrAddNum=767 or wrAddNum=1535 then
                                  readEnable <= source_ena;
                                end if;
                        else
                                readEnable <= '0';
                        end if;
                end if;
        end if;
end process;

-- write address
process(clk,aclr,writeEnable,sink_sop,sink_eop)
begin
        if aclr = '1' then
                internal_wrAddNum <= 1;
        else
                if rising_edge(clk) then -- using falling edge
                        if writeEnable = '1' then
                                if internal_wrAddNum = 1536 then
                                        internal_wrAddNum <= 1;
                                else
                                        internal_wrAddNum <= internal_wrAddNum + 1;
                                end if;
                        end if;
                end if;
        end if;
end process;

process(clk,internal_wrAddNum)
begin
    if falling_edge(clk) then
       wrAddNum<=internal_wrAddNum;
    end if;
end process;

-- read address
process(clk,aclr,source_ena,interval_sink_ena)
begin
        if aclr = '1' then
                rdAddNum <= 0;
        else
                if rising_edge(clk) then -- using falling edge
                        if readEnable_d0 = '1' then
                          if flag1='1' or flag2='1' then
                                case rdAddNum is
                                  when 0    => rdAddNum<=1;
                                  when 1536 => rdAddNum<=1;
                                  when 768  => rdAddNum<=769;  
                                  when 705 to 767|1473 to 1535
                                            => rdAddNum<=rdAddNum-703;  
                                  when others
                                            => rdAddNum <= rdAddNum + 64;
                                end case;  
                          end if;         
                        end if;
                end if;
        end if;
end process;

--internal_rdAddNum generate
process(clk,aclr,rdAddNum)
begin
        if aclr = '1' then
                internal_rdAddNum <= 0;
        else
                if falling_edge(clk) then
                   internal_rdAddNum<=rdAddNum;
                end if;
        end if;
end process;
-- --------------------------------------------------------------------------------
-- part4: Atlantic interface signals

-- generate sink_ena
sink_ena <= '1';

-- generate source_val
process(clk,readEnable_d0)
begin
        if falling_edge(clk) then -- using falling edge
           if flag1_d0='1' or flag2_d0='1' then
                  interval_source_val <= readEnable_d0;
                else
                  interval_source_val<='0';
           end if;       
        end if;
end process;

source_val <= interval_source_val;
-- --------------------------------------------------------------------------------
end structure;
--======================================================================
大家好，我是新人，学习FPGA时间不长，有段交织器程序，程序比较长，麻烦各位高手信心看，编译时说ram_Interleaver实体没定义，我不明白是怎么个意思？请知道原因的人帮小弟解答一下，不胜感激！