在状态机里加入并行向串行转换

我编了一段状态机的程序,想在s1状态时把send_bus[7:0]串行加载到send_si上,外部模块会保证s1经过10个clk
module send_core(clk,reset_n,send,send_over,sel_pv,sel_clk,reset_dt,
    reset_parts,ce_parts,overflow,send_si,sel_si,sel_out,recv,error,send_bus,parity);
inputclk,reset_n,send,overflow,parity;
input[7:0] send_bus;
output send_si, sel_si,sel_out,reset_parts,sel_clk,sel_pv,send_over,reset_dt,ce_parts,recv,error;
reg  send_si, sel_si,sel_out,reset_parts,sel_clk,sel_pv,send_over,reset_dt,ce_parts,recv,error;
reg  [1:0] state;
reg  [1:0] next_state;
reg  [9:0] send_buf;
parameters0=0,s1=1,s2=2,s3=3;
always@ (posedge clk or negedge reset_n)
begin
if(!reset_n)
  begin
   send_buf<=0;
  end
else
begin
   send_buf[0]<=0;
   send_buf[8:1]<=send_bus;
   send_buf[9]<=parity;
end
end

always @(posedge clk)
begin
  if(!reset_n)
   state<=s0;
  else state<=next_state;
end
always @( state or sendoroverfloworsend_over)
begin
  case(state)
  s0:
begin
  if(send) next_state<=s1;
  else next_state<=s0;
end
  s1:
begin
  if(overflow)next_state<=s2;
  else    next_state<=s1;
end
  s2:
begin
   if(overflow)next_state<=s3;
   else    next_state<=s2;
end
  s3: next_state<=s0;
  default:next_state<=s0;
endcase
end
always @(state)
begin
case(state)
   s0:begin
       reset_dt<=1;
       reset_parts<=0;
       ce_parts<=0;
       sel_si<=1;
       sel_clk<=0;
       sel_out<=0;
       sel_pv<=1;
       recv<=0;
       send_over<=0;
       error<=0;
      
      end
      
   s1:begin
       reset_parts<=1;
       ce_parts<=1;
       sel_si<=0;
       sel_clk<=1;
       sel_out<=0;
       sel_pv<=0;
       send_si<=send_buf>>1;
     end
              
   s2: begin
        sel_clk<=0;
        sel_out<=0;
        reset_parts<=1;
        ce_parts<=1;
        sel_si<=0;
        sel_pv<=0;

     end
      
   s3: begin
        send_over<=1;
        reset_parts<=0;
        ce_parts<=0;
     end
    default: begin
        reset_dt<=1;
        reset_parts<=0;
        ce_parts<=0;
        sel_si<=1;
        sel_clk<=0;
        sel_out<=0;
        sel_pv<=1;
        recv<=0;
        send_over<=0;
        error<=0;
      
      end

  endcase
  end
endmodule
编译时提示错误:
ignored unnecessaryinput"send_bus7"
ignored unnecessaryinput"send_bus6"
ignored unnecessaryinput"send_bus5"
ignored unnecessaryinput"send_bus4"
ignored unnecessaryinput"send_bus3"
ignored unnecessaryinput"send_bus2"
ignored unnecessaryinput"send_bus1"
ignored unnecessaryinput"parity"
请问是为什么

把<br>
&nbsp; &nbsp;&nbsp; &nbsp; send_buf[0]&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp; send_buf[8:1]&lt;=send_bus; <br>
&nbsp; &nbsp;&nbsp; &nbsp; send_buf[9]&lt;=parity;&nbsp;&nbsp;<br>
换成<br>
&nbsp; &nbsp;&nbsp; &nbsp; send_buf[9:0]&lt;={1'b0, send_bus[7:0],parity };