状态机，但是仿真显示状态不变化

状态机，但是仿真显示状态不变化
       



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity iic is
port(
clk:in std_logic;
rst:in std_logic;
ena:in std_logic;
clk_fp_out
       
ut std_logic;
complete
       
ut std_logic
);
end iic;
architecture structure of iic is
type states is(idle,start,addr_sel,addr_data,ack_s,write,stop);
signal current_state,next_state:states;
signal state_mask:std_logic_vector(3 downto 0);
signal clk_fp:std_logic;
signal cnt_byte:integer range 0 to 7;
begin
clk_fp_out<=clk_fp;
process(clk,rst)
variable cnt:std_logic_vector(7 downto 0);
begin
if(rst='1')then
  cnt:="00000000";
  clk_fp<='0';
elsif(clk'event and clk='1')then
   if(cnt="00001000"
       
then
    clk_fp<='1';
    cnt:="00000000";
   else
    if(ena='1')then
     cnt:=cnt+1;
    end if;
    clk_fp<='0';
   end if;
end if;
end process;
process(current_state,state_mask,cnt_byte)
begin
  case current_state is
   when idle=>
    next_state<=start;
    cnt_byte<=0;
    state_mask<="0000";
   when start=>
    next_state<=addr_sel;
    cnt_byte<=0;
    state_mask<="0001";
   when addr_sel=>
    if(cnt_byte=7)then
     next_state<=ack_s;
     cnt_byte<=0;
    else
     next_state<=addr_sel;
     cnt_byte<=cnt_byte+1;
    end if;
    state_mask<="0010";
   when addr_data=>
    if(cnt_byte=7)then
     next_state<=ack_s;
     cnt_byte<=0;
    else
     next_state<=addr_data;
     cnt_byte<=cnt_byte+1;
    end if;
    state_mask<="0011";
    when ack_s=>
     case state_mask is
      when "0010"=>next_state<=addr_data;
      when "0011"=>next_state<=write;
      when "0101"=>next_state<=stop;     
      when others=>null;
     end case;
     state_mask<="0100";
    when write=>
     if(cnt_byte=7)then
      next_state<=ack_s;
      cnt_byte<=0;
     else
      next_state<=write;
      cnt_byte<=cnt_byte+1;
     end if;
     state_mask<="0101";
   when stop=>
      next_state<=idle;
      cnt_byte<=0;
      state_mask<="0110";
  end case;
end process;
process(clk_fp,rst)
begin
if(rst='1')then
  current_state<=idle;
elsif(clk_fp'event and clk_fp='1')then
   current_state<=next_state;
end if;
end process;
process(current_state)
begin
  case current_state is
   when idle=>
    complete<='0';
   when start=>
    complete<='0';
   when addr_sel=>
    complete<='0';
   when addr_data=>
    complete<='0';
   when ack_s=>
    complete<='0';
   when write=>
    complete<='0';
   when stop=>
    complete<='1';
  end case;
end process;
end structure;