4664| 1
|
cpld中如何输出高阻态:引脚定义为inout,但是综合时出现错误 |
| ||
相关帖子 |
||
|小黑屋|手机版|Archiver|fpga论坛|fpga设计论坛
( 京ICP备20003123号-1 )
GMT+8, 2025-4-10 06:35 , Processed in 0.065575 second(s), 23 queries .
Powered by Discuz! X3.4
© 2001-2023 Discuz! Team.