编写高效的测试设计(testbenches)---8

VHDL例程
  以下是相当设计的VHDL测试文件，分别细分到独立的过程。
   
  Stimulus : process
  procedure addr_wr (address: in std_logic_vector(31 downto 0)) is
  begin
  data_addr_n <= ‘0’;
  we_rn <= ‘1’;
  ad <= address;
  end addr_wr;
  procedure data_wr (data_in: in std_logic_vector(31 downto 0 )) is
  begin
  data_addr_n <= ‘1’;
  we_rn <= ‘1’;
  ad <= data_in;
  end data_wr;
  procedure addr_rd (address: in std_logic_vector(31 downto 0)) is
  begin
  data_addr_n <= ‘0’;
  we_rn <= ‘0’;
  ad <= address;
  end addr_rd;
  procedure data_rd (data_in: in std_logic_vector(31 downto 0)) is
  begin
  data_addr_n <= ‘1’;
  we_rn <= ‘0’;
  ad <= data_in;
  end data_rd;
  procedure nop is
  begin
  data_addr_n <= ‘1’;
  we_rn = ‘0’;
  ad = ‘Z’;
  end nop;
  begin
  nop ; -- Nop
  wait for 200 ns;
  addr_wr (16#20340400#); -- Precharge, load Controller MR
  wait for 8 ns;
  data_wr (16#0704a076#); -- value for Controller MR
  wait for 8 ns;
  nop ; -- Nop
  wait for 40 ns;
  addr_wr (16#38000000#); -- Auto Refresh
  wait for 8 ns;
  data_wr (16#00000000#);
  wait for 8 ns;
  nop ; -- Nop
  ..
  ..
   
   
  细分激励到独立的任务使得激励很容易实现，也使得代码的可读性更好。
   
  在仿真时控制双向信号
  多数设计使用双向信号，在测试设计中必须区别对待双向信号和单向信号。
   
  VHDL示例
   
  The following is a VHDL bi-directional signal example:
  以下是一个vhdl描述的双向信号示例
   
  Library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.STD_LOGIC_UNSIGNED.all;
  entity bidir_infer is
  port (DATA : inout STD_LOGIC_VECTOR(1 downto 0);
  READ_WRITE : in STD_LOGIC);
  end bidir_infer;
  architecture XILINX of bidir_infer is
  signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0);
  begin
  process(READ_WRITE, DATA)
  begin
  if (READ_WRITE = ’1’) then
  LATCH_OUT <= DATA;
  end if;
  end process;
  process(READ_WRITE, LATCH_OUT)
  begin
  if (READ_WRITE = ’0’) then
  DATA(0) <= LATCH_OUT(0) and LATCH_OUT(1);
  DATA(1) <= LATCH_OUT(0) or LATCH_OUT(1);
  else
  DATA(0) <= ’Z’;
  DATA(1) <= ’Z’;
  end if;
  end process;
  end XILINX;
   
  为访问上例中的双向的DATA信号，一个测试可以设置如下：
   
  library ieee;
  use ieee.std_logic_1164.all;
  Entity testbench is
  End testbench;
  Architecture test_bidir of testbench is
  Component bidir_infer
  port (DATA : inout STD_LOGIC_VECTOR(1 downto 0);
  READ_WRITE : in STD_LOGIC);
  end component;
  signal read_writet: std_logic;
  signal datat, data_top : std_logic_vector(1 downto 0);
  begin
  datat <= data_top when (Read_writet = ’1’) else (others => ’Z’);
  data_top <= datat when (Read_writet = ’0’) else (others => ’Z’);
  uut : bidir_infer port map (datat, read_writet);
  process begin
  read_writet <= ’1’;
  data_top <= "10";
  wait for 50 ns;
  read_writet <= ’0’;
  wait;
  end process;
  end test_bidir;
   
  双向总线由测试台控制，双向总线的值可以通过数据顶层信号来访问。