vhdl代码在webpack6.2 下assigned package pins 时发生的问题？

为什么下面这段vhdl,在assigned package pins的时候 clock 脚没有出现在disign brows里？



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncomment the following lines to use the declarations that are
--provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity keyled is
  Port ( seg : out std_logic_vector(7 downto 0);
   sl : out std_logic_vector(3 downto 0);
   clock : in std_logic;
   keyin : in std_logic);
end keyled;

architecture Behavioral of keyled is
signal seg_reg : std_logic_vector(7 downto 0);    --mid signal
signal sl_reg:std_logic_vector(3 downto 0);
signal count_reg :  std_logic_vector(36 downto 0);
signal dispdat1 :  std_logic_vector(3 downto 0);
signal dispdat2 :  std_logic_vector(3 downto 0);
signal keylast_reg :std_logic; --_vector(7 downto 0); --mid signal
signal keycur_reg :std_logic;--_vector(7 downto 0); --mid signal
signal delay :std_logic_vector(1 downto 0); --mid signal
--signal delay2 :std_logic_vector; --mid signal

begin
process (clock) --count_reg inc 1
begin
  if clock 'event and clock='1' then
   delay(0)<= count_reg(15);
    delay(1)<= count_reg(5);
   count_reg<=count_reg+1;
  end if ;

end process ;

keycur_reg<=keyin;

process (delay(0))        --scan key process(delay1)
  
  begin
  if (keylast_reg/=keycur_reg) then
   keylast_reg<=keycur_reg;
    dispdat1<="0001";
  end if;
end process;

--with keylast_reg select
--dispdat2<="1010" when "1",
--    "1011" when "0";

process(keylast_reg)
begin
if(keylast_reg='1') then
     dispdat2<="1010";
    else
    dispdat2<="1011";
    end if;
end process;


process (sl_reg)   --display scan
begin
  if (sl_reg="0111")then
  case dispdat1 is
    when "0000"=>seg_reg<="11000000";
    when "0001"=>seg_reg<="11111001";
    when "0010"=>seg_reg<="10100100";
    when "0011"=>seg_reg<="10110000";
    when "0100"=>seg_reg<="10011001";
    when "0101"=>seg_reg<="10010010";
    when "0110"=>seg_reg<="10000010";
    when "0111"=>seg_reg<="11111000";
    when "1000"=>seg_reg<="10000000";
    when "1001"=>seg_reg<="10010000";
    when "1010"=>seg_reg<="10001000";
    when "1011"=>seg_reg<="10000011";
    when "1100"=>seg_reg<="11000110";
    when "1101"=>seg_reg<="10100001";
    when "1110"=>seg_reg<="10000110";
    when "1111"=>seg_reg<="10001110";
        when others=>seg_reg<="10001110";
  end case;
  elsif (sl_reg="1011") then
   case dispdat2 is
    when "0000"=>seg_reg<="11000000";
    when "0001"=>seg_reg<="11111001";
    when "0010"=>seg_reg<="10100100";
    when "0011"=>seg_reg<="10110000";
    when "0100"=>seg_reg<="10011001";
    when "0101"=>seg_reg<="10010010";
    when "0110"=>seg_reg<="10000010";
    when "0111"=>seg_reg<="11111000";
    when "1000"=>seg_reg<="10000000";
    when "1001"=>seg_reg<="10010000";
    when "1010"=>seg_reg<="10001000";
    when "1011"=>seg_reg<="10000011";
    when "1100"=>seg_reg<="11000110";
    when "1101"=>seg_reg<="10100001";
    when "1110"=>seg_reg<="10000110";
    when "1111"=>seg_reg<="10001110";
        when others=>seg_reg<="10001110";
  end case;

  end if;
end process;


process(delay(1))
  begin
  if (sl_reg="0111") then
    sl_reg<="1011";
   --elsif(sl_reg="1011") then
   --sl_reg<="0111";
   else
    sl_reg<="0111";
   end if;
end process ;

sl<=sl_reg;
seg<=seg_reg;


end Behavioral;