illegal Procedural Assignment 怎么修改啊

我的波特率发生器程序
module baud (clk,resetb,bclk);//产生UART波特率的16倍频
input clk;
input resetb;
output bclk;
reg cnt;
[email=always@(posedge]always@(posedge[/email] clk or negedge resetb)
begin
if (resetb) //复位
begin
  cnt=0;bclk=0;
end
else
begin if (clk)
  begin
  //if cnt>=260 begin cnt:=0;bclk<='1';end//根据UART波特率设置分频系数
  if (cnt>=7)
   begin cnt=0;bclk=1;end//根据UART波特率设置分频系数
  else begin cnt=cnt+1;bclk=0;end
  end
end
end
endmodule

怎么出现以下错误？
Error (10137): Verilog HDL Procedural Assignment error at baud.v(20): illegal Procedural Assignment to nonregister data type "bclk"