VHDL syntax error at counter10.vhd(32) near

Error (10500): VHDL syntax error at counter10.vhd(32) near text "process";expecting "if"

就是说
end process;
这句话有问题
我的源程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
   port (clk:in std_logic;
     reset:in std_logic;
     din:in std_logic_vector(3 downto 0);
     dout
       
ut std_logic_vector(3 downto 0);
     c
       
ut std_logic);
end counter10;

architecture Behavioral of counter10 is
signal count:std_logic_vector(3 downto 0);
begin
dout<=count;
process(clk,reset,din)
begin
if reset='0' then
  count<=din;
  c<='0';
  else if rising_edge(clk) then
    if count="1001" then
     count<="0000";
     c<='1';
     else
     count<=count+1;
     c<='0';
     end if;
   end if;
end process;
end Behavioral;

请帮忙指点一下怎么改

错误很简单!<br>
但不太容易看!<br>
错误就是 ELSE IF<br>
要么改成IF-ELSIF-END IF组合<br>
要么再加一个END IF;

else if 改成 ELSIF 啊~~~~~~~<br>
elsif rising_edge(clk) then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;elsif count="1001" then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;count&lt;="0000";<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;c&lt;='1';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; else<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;count&lt;=count+1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;c&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; end if;

我在软件上试了一下，这样可以运行，本人也是刚学maxplus2的菜鸟啊～～～～～～<br>
library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_arith.all;<br>
use ieee.std_logic_unsigned.all;<br>
entity counter10 is<br>
&nbsp; &nbsp;&nbsp; &nbsp; port (clk:in std_logic;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; reset:in std_logic;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; din:in std_logic_vector(3 downto 0);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; dout
       
ut std_logic_vector(3 downto 0);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; c
       
ut std_logic);<br>
end counter10;<br>
<br>
architecture Behavioral of counter10 is<br>
&nbsp; &nbsp;&nbsp;&nbsp;signal count:std_logic_vector(3 downto 0);<br>
begin<br>
&nbsp; &nbsp;&nbsp;&nbsp;dout&lt;=count;<br>
<br>
process(clk)<br>
begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;if rising_edge(clk) then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; if count="1001" then<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;count&lt;="0000";<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;c&lt;='1';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; else<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;count&lt;=count+1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;c&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; end if;<br>
&nbsp; &nbsp;&nbsp; &nbsp; end if;<br>
end process;<br>
end Behavioral;