异步FIFO疑问

module async(aempty_n, afull_n, wptr, rptr, wrst_n);
output aempty_n, afull_n;
input [3:0] wptr, rptr;
input wrst_n;
reg direction;
wire high = 1'b1;
wire dirset_n = ~((wptr[3]^rptr[2]) & ~(wptr[2]^rptr[3]));
wire dirclr_n = ~((~(wptr[3]^rptr[2])&(wptr[2]^rptr[3])) | ~wrst_n);
always @(posedge high or negedge dirset_n or negedge dirclr_n)
if (!dirclr_n)
direction <= 1'b0;
else if (!dirset_n)
direction <= 1'b1;
else
direction <= high;


assign aempty_n = ~((wptr == rptr) && !direction);
assign afull_n = ~((wptr == rptr) && direction);
endmodule

字符串 high 做什么用的?不理解