串并转换改错，请大家指出

module stop(dataout,clk,datai);
output[7:0] dataout;
input datain;
input clk;
reg[7:0] dataout;
reg[7:0] mem;
reg[3:0] i,j,k;
initial
begin
i<=0;
j<=0;
end
always @(negedge clk)
begin
if(j==7)
begin
j<=0;
k<=1;
end
else
begin
j<=j+1;
k<=0;
end
end

always @(posedge clk)
begin
mem[0]<=datain;
for(i=0;i>=6;i=i+1)
begin
mem[i+1]<=mem;
end
end

always @(posedge k)
begin
dataout<=mem;
end
endmodule