5分频（占空比3：2）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY DIV55 IS
PORT(
  CLK:INSTD_LOGIC;
COUT: OUTSTD_LOGIC
);
END DIV55;

ARCHITECTURE BEHAVIORAL OF DIV55 IS
SIGNAL COUNTER: STD_LOGIC_VECTOR(2 DOWNTO 0):="001";
BEGIN
PROCESS(CLK)
  BEGIN
IF CLK'EVENT AND CLK='1' THEN
COUNTER<=COUNTER+1;
IF COUNTER="101" THEN
COUNTER<="001";
END IF;
END IF;
END PROCESS;
COUT<=COUNTER(2);
END BEHAVIORAL

谢谢，学到东西了

还是verilog的代码量少！！