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用fpga控制步进电机如何设计

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ngtim 发表于 2010-6-28 00:19:55 | 显示全部楼层 |阅读模式
用fpga控制步进电机如何设计

哪位仁兄,提供一些源程序,部分也好.或能给点资料,指导指导
longt 发表于 2010-6-28 01:26:57 | 显示全部楼层
任意关于此方面的源程序或其他资料,提示<br>
都不甚感谢
HDL 发表于 2010-6-28 01:57:26 | 显示全部楼层
我也想要啊,不过我知道有本书上有.明天去借过来.嘿嘿^
interig 发表于 2010-6-28 03:50:19 | 显示全部楼层
我也想要啊,<br>
<br>

        zhang18jun@163.com
longtime 发表于 2010-6-28 04:23:40 | 显示全部楼层
这个用有限状态机能实现吧?
VVIC 发表于 2010-6-28 05:33:57 | 显示全部楼层
你搜索下关于 PWM方面的资料吧
CHANG 发表于 2010-6-28 07:19:48 | 显示全部楼层
建议到图书馆找几本书看看,很多实例教程都有这方面的例子
       
CHAN 发表于 2010-6-28 08:59:40 | 显示全部楼层
是用有限状态机,我做过的<br>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<br>
设计三相磁阻式转子步进电机控制器<br>
产生对A/B/C三相绕组的控制信号<br>
在控制信号控制下分别完成三相双三拍正转和三相六拍反转<br>
做出状态跳变图(通电为1,不通电为0<br>
<br>
输入信号:rst_.复位信号,低电平有效<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; clk,时钟信号<br>
      mode,控制信号,1三相双三拍正转,0三 <br>
       相六拍反转<br>
输出信号:outa,a绕组驱动信号<br>
      outb,b绕组驱动信号<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; outc,c绕组驱动信号<br>
<br>
<br>
代码:<br>
module step_engineer(clk,rst_,mode,outa,outb,outc);<br>
input clk,rst_,mode;<br>
output outa,outb,outc;<br>
reg outa,outb,outc;<br>
reg [2:0] state,next_state;<br>
parameter IDLE=3'b000, A=3'b100, B=3'b010, C=3'b001, AB=3'b110, BC=3'b011, CA=3'b101;<br>
always@(posedge clk or negedge rst_)<br>
if(!rst_)<br>
&nbsp;&nbsp;state&lt;=IDLE;<br>
else<br>
&nbsp;&nbsp;state&lt;=next_state;<br>
always@(state or rst_ or mode)<br>
if(!rst_)<br>
next_state=IDEL;<br>
else if(mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=AB;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase<br>
<br>
else if(!mode)<br>
case(state)<br>
&nbsp;&nbsp;IDLE: next_state=A;<br>
&nbsp;&nbsp;A: next_state=CA;<br>
&nbsp;&nbsp;CA: next_state=C;<br>
&nbsp;&nbsp;C: next_state=BC;<br>
&nbsp;&nbsp;BC: next_state=B;<br>
&nbsp;&nbsp;B: next_state=AB;<br>
&nbsp;&nbsp;AB: next_state=A;<br>
&nbsp;&nbsp;default: next_state=IDLE;<br>
endcase
CCIE 发表于 2010-6-28 10:34:15 | 显示全部楼层
always@(posedge clk or negedge rst_)<br>
if(!rst_)<br>
{outa,outb,outc}&lt;=3'd0;<br>
else<br>
{outa,outb,outc}&lt;=state;<br>
endmodule
ICE 发表于 2010-6-28 11:10:33 | 显示全部楼层
我这里好像有个pwm的fpga实验图,你们看看。
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