麻烦各位给修改下,我这个实现不了输出的结果,结果直接置位高低电平了..

麻烦各位给修改下,我这个实现不了输出的结果,结果直接置位高低电平了..


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity control_4 is
port(  clk: instd_logic;  
   linesy: instd_logic;
  pixelena: out std_logic;
   lineena: out std_logic);
end control_4;
architecture rtl of control_4 is
signal pixelcount:integer;
begin
process(pixelcount,clk,linesy)
  begin
  if linesy='0' then
   null;--pixelcount<=0;
  elsif rising_edge(clk) then
   if(pixelcount=4064) then
    pixelcount<=0;
    lineena<='1';
    pixelena<='0';
   else
    pixelcount<=pixelcount+1;  --行计数
   end if;
  end if;
end process;
end rtl;

出现下面的错误:

Warning: Reduced register "lineena~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "pixelena~reg0" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
Warning: Pin "pixelena" stuck at GND
Warning: Pin "lineena" stuck at VCC
Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "linesy"



谢谢各位了啊~

不会吧~哪位大大帮下忙啊

用什么软件仿真的？