verilog新手求助

开始学verilog,编写了一段直流电机控速的程序，编译时没错，但程序达不到要求，请各位高手帮忙看下到底是什么问题。
我想实现的功能是（speed_now<th_speed）是强加速，((th_speed<=speed_now)&(speed_now<=target_speed))使弱加速，speed_now==target_speed是定速，target_speed<=speed_now是减速
module zjm(reset,clk,speed_now,th_speed,target_speed,pwme,phase,flag);
input reset,clk;
input [7:0] speed_now,th_speed,target_speed;
output pwme;
output phase,flag;
reg pwme,phase,flag;
//reg [7:0] speed_now,th_speed,target_speed;
reg [2:0] clk_125,clk_375,clk_500;
always@(posedge clk or posedge reset)
begin
// clk<=~clk
if(reset==1)
begin
  pwme<=1;
  clk_125<=1;clk_375<=3;clk_500<=4;phase<=1;
end
else
if(phase==1)
begin
// case(speed_now)
  if(speed_now<th_speed)
  begin
  clk_125<=1;clk_375<=3;clk_500<=4;
  pwme<=1;
  end
  else
begin
  if((th_speed<=speed_now)&(speed_now<=target_speed))
   begin
  clk_125<=1;clk_375<=clk_375-1;clk_500<=4;
  pwme<=1;
   end
  else
  begin
   if(speed_now==target_speed)
    begin
    clk_500<=clk_500-1;clk_375<=3;clk_125<=1;
    pwme<=1;flag<=1;
    end
   else
    begin
   if(target_speed<=speed_now)
    begin
     clk_500<=4;clk_375<=clk_375-1;clk_125<=1;
      pwme<=0;
   end
    end
   end
   end
// end case;
  if((clk_500==0) | (clk_375==0))
  begin
   clk_500<=4;clk_375<=3;phase<=0;
  end
  end
else
  if(phase==0)
begin
//case(speed_now)
  if(speed_now<=th_speed)
begin
clk_500<=4;clk_375<=3;clk_125<=1;
pwme<=1;
end
  else
begin
if((th_speed<=speed_now)&(speed_now<=target_speed))
begin
clk_500<=4;clk_375<=3;clk_125<=clk_125-1;
pwme<=0;
end
  else
  begin
if(speed_now==target_speed)
begin
clk_500<=clk_500-1;clk_375<=3;clk_125<=1;
pwme<=0;
end
  else
  begin
if(target_speed<=speed_now)
begin
clk_500<=4;clk_375<=3;clk_125<=clk_125-1;
pwme<=1;
end
  end
   end
  end
  //end case;
if((clk_125==0)|(clk_500==0))
  begin
  clk_125<=1;clk_500<=4;phase<=1;
  end
end
end
endmodule

我的主要问题就是clk_125,和clk_500这两个技术器没有反应

把这几个模块分别编译仿真试一下？？