请帮忙看一下我的错误

我在设计频率计中的控制器时碰到的问题


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CONTROL is
  Port ( CLK : in std_logic;
   RSET : in std_logic;
   EN : out std_logic;
   CLR : out std_logic;
LOAD : out std_logic);
end CONTROL;
architecture Behavioral of CONTROL is
SIGNAL A: std_logic;
begin
P1:
PROCESS(CLK,RSET)
BEGIN
IF (RSET='1')THEN
EN<='0';
LOAD<='0';
CLR<='0';
A<='1';
ELSIF (CLK'EVENT AND CLK='1')THEN
A<=NOT A;
END IF;
END PROCESS;
P2:
PROCESS(CLK,A)
BEGIN
IF(CLK='0' AND A='0')THEN
CLR<='1';
ELSE
CLR<='0';
END IF;
END PROCESS;
LOAD<=NOT A;
EN<=A;
end Behavioral;
错误如下：
WARNING:Xst:528 - Multi-source in Unit <control> on signal <CLR> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <control> on signal <A> not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <control> on signal <LOAD> not replaced by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed
CPU : 1.67 / 3.14 s | Elapsed : 2.00 / 3.00 s