begin<br>
counter: process(reset,clk,shift_start)<br>
begin<br>
if(reset = '0') then<br>
cnt <= (others => '0');<br>
elsif(clk'event and clk = '1') then<br>
if(shift_start = '0') then<br>
cnt <= cnt + 1;<br>
else<br>
cnt <= (others => '0');<br>
end if;<br>
end if;<br>
end process counter;<br>
<br>
fsm: block<br>
begin<br>
sync: process(reset,clk)<br>
begin<br>
if(reset= '0') then<br>
current_state <= idle;<br>
elsif(clk'event and clk = '1') then<br>
current_state <= next_state;<br>
end if;<br>
end process sync;<br>
<br>
comb: process(current_state,cnt,start)<br>
begin<br>
case current_state is<br>
when idle =><br>
ready <= '0';<br>
reg_en <= '1';<br>
shift_start <= '1';<br>
data_valid <= '1';<br>
if(start = '0') then<br>
reg_en <= '0';<br>
next_state <= recieve;<br>
else<br>
next_state <= idle;<br>
end if;<br>
when recieve =><br>
reg_en <= '1';<br>
ready <= '1';<br>
data_valid <= '0';<br>
shift_start <= '0';<br>
next_state <= shift;<br>
when shift =><br>
reg_en <= '1';<br>
ready <= '1';<br>
data_valid <= '0';<br>
if(cnt = 8) then<br>
shift_start <= '1';<br>
next_state <= finish;<br>
else<br>
shift_start <= '0'; <br>
next_state <= shift;<br>
end if;<br>
when finish =><br>
reg_en <= '1';<br>
ready <= '0';<br>
data_valid <= '1';<br>
shift_start <= '1';<br>
next_state <= idle;<br>
when others =><br>
next_state <= idle;<br>
end case;<br>
end process comb;<br>
<br>
end block fsm;<br>
<br>
data_channel: process(reset,clk)<br>
begin<br>
if(reset = '0') then<br>
reg <= (others => '0');<br>
q <= '0';<br>
elsif(clk'event and clk = '1') then<br>
if(reg_en = '0') then<br>
reg <= data_in;<br>
elsif(shift_start = '0') then<br>
q <= reg(7);<br>
for i in 7 downto 1 loop --shift register<br>
reg(i) <= reg(i - 1);<br>
end loop;<br>
reg(0) <= '0';<br>
else <br>
q <= '0';<br>
end if;<br>
end if;<br>
end process data_channel; <br>
<br>
end Behavioral;<br>
<br>
并串转换,,整个代码已经通过了后仿真,而且思路还是比较清楚的,可靠性和稳定性方面也应该没有问题滴,呵呵。不过说老实话,里面有些信号是确实可以去掉的,不过后来就懒得改了。如果谁想要实际的工程中用的话可以改一下。 |