请教串并并串转换原理

偶也是新手

--串并转换8比特<br>
--同步置零<br>
--8位数据输出<br>
library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_unsigned.all;<br>
entity serial_to_line is<br>
port(clk,reset,data:in std_logic;<br>
&nbsp; &nbsp; &nbsp; &nbsp;&nbsp;&nbsp;outdata: out std_logic_vector(7 downto 0));<br>
end serial_to_line;<br>
<br>
architecture behave of serial_to_line is<br>
signal reg_data: std_logic_vector(7 downto 0);<br>
signal reg_count:integer range 8 downto 0;<br>
begin<br>
process(clk)<br>
variable reg_data1:std_logic_vector(7 downto 0);<br>
begin<br>
<br>
if rising_edge(clk) then <br>
&nbsp;&nbsp;case reset is<br>
&nbsp;&nbsp;when '0'=&gt;&nbsp;&nbsp;outdata&lt;="00000000";<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;reg_data&lt;="00000000";<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;reg_count&lt;=0;<br>
&nbsp;&nbsp;when '1'=&gt;&nbsp;&nbsp;reg_data1:=reg_data;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;reg_data1:=data&amp;reg_data1(7 downto 1);<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;case reg_count is<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;when&nbsp;&nbsp;7 =&gt; reg_count&lt;=0;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; <br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; outdata&lt;=reg_data1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; reg_data&lt;=reg_data1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;when others=&gt; reg_count&lt;=reg_count+1;&nbsp; &nbsp; &nbsp; &nbsp; <br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; reg_data&lt;=reg_data1; <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;end case;<br>
&nbsp;&nbsp;when others=&gt;NUll;<br>
&nbsp;&nbsp;end case;<br>
end if; <br>
--reg_data&lt;=reg_data1;<br>
end process;<br>
end architecture behave;

看uart的说明文档

哪里有74165的例子呢？

我自己写的，给点意见