简易数字钟代码 vhdl

简易数字钟代码学校做实验用的直接输出bcd码  在外接一个数码管译码程序就可以

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port(clk ,rst:in std_logic;
  sa,sb,ma,mb,ha,hb

ut std_logic_vector(3 downto 0));
end ;
architecture one of cnt is
signal cnt1,cnt2 :std_logic:='0';
begin
-------------------------------秒计时-------------------
process(clk,rst)
variableqsa,qsb : std_logic_vector(3 downto 0);
begin
if rst='1' thenqsa:=(others=>'0');
       qsb:=(others=>'0');
elsif clk'event and clk='1' then
  if (qsa=9 and qsb=5)then cnt1<='1';qsa:=(others=>'0');qsb:=(others=>'0');
  elsif qsa=9then qsa:=(others=>'0');
  if qsb=5 thenqsb:=(others=>'0');
  else qsb:=qsb+1;
  end if;
elseqsa:=qsa+1;cnt1<='0';
end if;
end if;

sb<=qsb;
sa<=qsa;
end process;
----------------------------------分计时-------------------------
process(cnt1,rst)
variableqma,qmb : std_logic_vector(3 downto 0);
begin
if rst='1' thenqma:=(others=>'0');
     qmb:=(others=>'0');
elsif cnt1'event and cnt1='1' then
if (qma=9 and qmb=5)then cnt2<='1';qma:=(others=>'0');qmb:=(others=>'0');
elsif qma=9then qma:=(others=>'0');
  if qmb=5 thenqmb:=(others=>'0');
  else qmb:=qmb+1;
  end if;
else qma:=qma+1;cnt2<='0';
end if;
end if;
mb<=qmb;
ma<=qma;
end process;
------------------------------------小时计时-------------------
process(cnt2,rst)
variableqha,qhb : std_logic_vector(3 downto 0);
begin
if rst='1' thenqha:=(others=>'0');
     qhb:=(others=>'0');
elsif cnt2'event and cnt2='1' then
if (qha=3 and qhb=2) then qha:=(others=>'0');qhb:=(others=>'0');
elsifqha=9 then qha:=(others=>'0');
   if (qhb=2 and qha=3) then qhb:=(others=>'0');qha:=(others=>'0');
   else qhb:=qhb+1;
   end if;
elseqha:=qha+1;
end if;  
end if;
hb<=qhb;
ha<=qha;
end process;
end one;