moduletes_czb;
reg tb_clk;
reg tb_reset;
reg tb_en;
wire tb_odd;
wire tb_even;
wire [7:0]tb_out;
reg tb_in;
always #50 tb_clk<=~tb_clk;
initial
begin
tb_in<=1;
tb_clk<=0;
tb_reset<=1;
#90 tb_reset<=0;
tb_en<=1;
#90 tb_in<=1;
#90 tb_in<=0;
#90 tb_in<=0;
#90 tb_in<=1;
#90 tb_in<=0;
#90 tb_in<=1;
#90 tb_in<=0;
#90 tb_in<=1;
repeat(50)
begin
tb_reset<={$random}%2;
tb_en<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
#90 tb_in<={$random}%2;
end
end
serial_pal aa(.clk(tb_clk),.reset(tb_reset),.en(tb_en),.in(tb_in),.out(tb_out),.odd(tb_odd),.even(tb_even));
initial
begin
$monitor($time,,,"tb_en%b,tb_in%b,tb_out%b,tb_reset%b,tb_odd%b,tb_even%b",tb_en,tb_in,tb_out,tb_reset,tb_odd,tb_even);
end
endmodule
测试过了
不过初学这个,不知有无错误 |