testbench的写法，这样写是规范的么？

学习了!!!!!!!!!!!!!!!!!!!!!!!!

公司里的规范是这样啊。<br>
不错，感谢11楼的。

因为看得书也不是很多，见过的testbench都是定义类型和赋初值分开的，<br>
而且觉得这一段<br>
wire [7:0] temp={dout[1:0],dout[7:2]};<br>
always @(posedge clk or negedge nrst)<br>
if (~nrst)&nbsp; &nbsp;&nbsp; &nbsp; dout&lt;=0;<br>
else if (sel==1) dout&lt;=din;<br>
else&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; dout&lt;=temp;<br>
很别扭！<br>
多谢给位，尤其是11# ！！！<br>
比较习惯这样写：<br>
`define clk_cycle 10<br>
module ex2_6;<br>
//test bench<br>
<br>
reg clk;<br>
reg nrst;<br>
reg sel;<br>
reg [7:0] din;<br>
reg [7:0] temp;<br>
wire [7:0] dout;<br>
<br>
always `clk_cycle clk=~clk;<br>
<br>
assign dout=temp;<br>
<br>
initial begin<br>
&nbsp; &nbsp; &nbsp; &nbsp; clk=0;<br>
&nbsp; &nbsp; &nbsp; &nbsp; nrst=1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; sel=0;<br>
&nbsp; &nbsp; &nbsp; &nbsp; [7:0] din=0;<br>
end<br>
<br>
initial begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;#50 nrst=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;#70 nrst=1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;#80 sel=1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;#15 sel=0;<br>
end<br>
<br>
integer seed=4;<br>
<br>
always@(posedge clk)<br>
din&lt;=#1 $random(seed);<br>
<br>
always @(posedge clk or negedge nrst)<br>
if (~nrst)&nbsp; &nbsp;&nbsp; &nbsp; temp&lt;=0;<br>
else if (sel==1) temp&lt;=din;<br>
else&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; temp&lt;={temp[1:0],temp[7:2]};<br>
<br>
endmodule<br>
<br>
[ 本帖最后由 bonesoul 于 2006-8-14 20:05 编辑 ]

受教了，继续学习

感谢11楼提供的代码书写规范，哈哈，由长知识了。
       

没看出不规范的

有所收获！

just so so...

没什么问题

多谢大侠指教