怎么用数据流描述????
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY cmp IS
PORT(A1,B1,A0,B0:IN STD_LOGIC;
Y1,Y2,Y3:OUT STD_LOGIC);
END ENTITY cmp ;
ARCHITECTURE one OF cmp IS
BEGIN
PROCESS(A1,B1,A0,B0)
BEGIN
IF A1>B1 THEN
Y1<='1';
ELSIF (A1=B1) AND A0>B0 THEN
Y2<='1';
ELSIF A1<B1 THEN
Y3<='1';
END IF;
END PROCESS;
ENDARCHITECTUREone ;
推荐几本可以在网上下的VHDL的书吧!!!!