verilog例子1X2的选通器

verilog例子1X2的选通器

1X2的选通器，choose决定输入信号Sign_in从A或B端口输出，得不到想要的结果！
代码如下：
module Select(En,Choose,Sign_in,Out_A,Out_B);
    input En,Choose,Sign_in;
    output Out_A,Out_B;
    reg Out_A,Out_B;
always @ (posedge En)
    if (En==1)
        begin
          if (Choose==0)
           begin
                 Out_A=Sign_in;
                 Out_B=0;
           end
          else
           begin
           Out_B=0;
                 Out_B=Sign_in;
               end
        end
endmodule

posedge en？<br>
那样只能执行一次哦<br>
&nbsp; &nbsp;Out_B=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; Out_B=Sign_in;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
<br>
而且得等其他choose啊什么的准备好了<br>
再posedge en才有效

同意楼上 ..是不是应该加个 clk

看看你代码的这里：<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;Out_B=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; Out_B=Sign_in;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end

...如果改成 always@(en==1) <br>
<br>
然后把第一个if 去掉 怎么样??

module example( Out_A , Out_B , Sign_In , Sel , En );<br>
<br>
output Out_A;<br>
output Out_B;<br>
input Sign_In;<br>
input Sel;<br>
input En;<br>
<br>
assign Out_A = En &amp; Sel &amp; Sign_In;<br>
assign Out_B = En &amp; ~Sel &amp; Sign_In;<br>
<br>
endmodule

六楼写的精悍

牛人！看来得好好学习了。

always @（en or choose or sign_in）

牛人呀,看来得好好学习