VHDL实现16位精度锯齿波

-----------------------------------------------------
---------------16位精度锯齿波VHDL实现----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package sim is
component ncoaw
port( reset :in std_logic;
   clk :in std_logic;
   sync:in std_logic;
   freq:in std_logic_vector(15 downto 0);
   saw_out: out std_logic_vector(7 downto 0)
  );
end component;
end sim;
-----------------------------------------------------
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.sim.all;
entity ncosaw is
  port( reset :in std_logic;
   clk :in std_logic;
   sync:in std_logic;--同步信号，当sync为1时，相位累加器清0
   freq:in std_logic_vector(15 downto 0);--输入频率值
   saw_out: out std_logic_vector(7 downto 0)
  );
end ncosaw;
architecture arch_ncosaw of ncosaw is
signal phase:std_logic_vector(15 downto 0);--相位累计器的存储器，将每次累加的结果保存起来
constant max_phase:std_logic_vector(13 downto 0):=(others=>'1');
constant output_zeros:std_logic_vector(7 downto 0):=(others=>'0');
signal sin_index:std_logic_vector(7 downto 0);
signal sin_table:std_logic_vector(7 downto 0);
signal phase_d1:std_logic_vector(1 downto 0);
signal phase_d2:std_logic_vector(1 downto 0);
signal cos_index:std_logic_vector(13 downto 0);
signal cos_table:std_logic_vector(7 downto 0);
begin
process(reset,clk)
begin
if reset='1' then
  phase<=(others=>'0');
elsif clk'event and clk='1' then
if sync='1' then
   phase<=(others=>'0');
else
   phase<=phase+freq;
end if;
end if;
end process;
saw_out<=phase(15 downto 8);
end arch_ncosaw;
编译通过！！

50MHz工作频率下的仿真波形

顶原创，搂住可以考虑在输出正弦信号的

...<br>
&nbsp;&nbsp;楼主&nbsp; &nbsp; 输出明显是8位&nbsp; &nbsp;<br>
&nbsp; &nbsp; 实现了16位精度？<br>
&nbsp;&nbsp;还有：<br>
&nbsp; &nbsp;signal phase:std_logic_vector(15 downto 0);--相位累计器的存储器，将每次累加的结果保存起来<br>
constant max_phase:std_logic_vector(13 downto 0):=(others=&gt;'1');<br>
constant output_zeros:std_logic_vector(7 downto 0):=(others=&gt;'0');<br>
signal sin_index:std_logic_vector(7 downto 0);<br>
signal sin_table:std_logic_vector(7 downto 0);<br>
signal phase_d1:std_logic_vector(1 downto 0);<br>
signal phase_d2:std_logic_vector(1 downto 0);<br>
signal cos_index:std_logic_vector(13 downto 0);<br>
signal cos_table:std_logic_vector(7 downto 0);<br>
&nbsp;&nbsp;这些又是怎么回事？&nbsp; &nbsp;: )

原帖由 ljmdiy 于 2007-2-3 15:17 发表<br>
...<br>
&nbsp;&nbsp;楼主&nbsp; &nbsp; 输出明显是8位&nbsp; &nbsp;<br>
&nbsp; &nbsp; 实现了16位精度？&nbsp;&nbsp;还有：<br>
&nbsp; &nbsp;signal phase:std_logic_vector(15 downto 0);--相位累计器的存储器，将每次累加的结果保存起来<br>
constant max_phase:std_logic_vector(13 ... LZ的程序中，虽然输出时8位（这可能是为了和外部的8位DAC配合），但在内部保留了16位的相位计数，<br>
<br>
所以LZ的16位精度应该明确的说是16位相位精度而不是信号幅度精度

原帖由 liushui666 于 2007-1-26 11:02 发表<br>
50MHz工作频率下的仿真波形
       
<br>
可能我的眼拙，似乎你这个波形看不出什么来。

不错,参考参考

原帖由 dianzi 于 2007-2-4 16:46 发表<br>
<br>

       
<br>
可能我的眼拙，似乎你这个波形看不出什么来。 从数字上来说,的确不象锯齿哦,是不是后面数字输出后还要进行处理变化一下啊,楼主能解释一下吗?

constant max_phase:std_logic_vector(13 downto 0):=(others=&gt;'1');<br>
constant output_zeros:std_logic_vector(7 downto 0):=(others=&gt;'0');<br>
signal sin_index:std_logic_vector(7 downto 0);<br>
signal sin_table:std_logic_vector(7 downto 0);<br>
signal phase_d1:std_logic_vector(1 downto 0);<br>
signal phase_d2:std_logic_vector(1 downto 0);<br>
signal cos_index:std_logic_vector(13 downto 0);<br>
signal cos_table:std_logic_vector(7 downto 0);<br>
<br>
<br>
这些似乎只有定义啊&nbsp; &nbsp;～～～<br>
&nbsp;&nbsp;LZ能给个说明吗？

library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_arith.all;<br>
use ieee.std_logic_unsigned.all;<br>
package sim is<br>
&nbsp;&nbsp;component ncoaw<br>
&nbsp; &nbsp;port( reset :in std_logic;&nbsp;&nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;clk&nbsp; &nbsp;:in std_logic;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sync&nbsp;&nbsp;:in std_logic;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;freq&nbsp;&nbsp;:in std_logic_vector(15 downto 0);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;saw_out: out std_logic_vector(7 downto 0)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;);<br>
&nbsp;&nbsp;end component;<br>
end sim;<br>
<br>
这个package有需要吗？<br>
<br>
LZ的代码里不是有这段：<br>
entity ncosaw is<br>
&nbsp; &nbsp; port( reset :in std_logic;&nbsp;&nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;clk&nbsp; &nbsp;:in std_logic;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sync&nbsp;&nbsp;:in std_logic;--同步信号，当sync为1时，相位累加器清0<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;freq&nbsp;&nbsp;:in std_logic_vector(15 downto 0);--输入频率值<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;saw_out: out std_logic_vector(7 downto 0)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;);<br>
end ncosaw;<br>
-----------------------------<br>
-----------------------------<br>
看下面这个<br>
library work;<br>
use work.sim.all;<br>
这样写还有意义吗？ 有必要吗？<br>
&nbsp;&nbsp;有点蒙了....&nbsp; &nbsp;
       
<br>
<br>
望大侠赐教～～～<br>
<br>
[ 本帖最后由 ljmdiy 于 2007-2-7 18:04 编辑 ]