我做了一个双向缓冲器，仿真的时候不对，大家帮忙看看

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TRIGATE IS
PORT
(
ADDR1:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDR2:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DIRR:IN STD_LOGIC;   --控制读时，addr1为输出，addr2为输入
DIRW:IN STD_LOGIC   --控制读时，addr2为输出，addr1为输入

);
END TRIGATE;

ARCHITECTURE A OF TRIGATE IS
BEGIN
PROCESS(DIRR,DIRW)
BEGIN
IF(DIRR='0')THEN
ADDR1 <= ADDR2;
ELSIF(DIRW='0')THEN
ADDR2 <= ADDR1;
END IF;
END PROCESS;
END A;

你这样写好像不行，双向端口若作输入时，其输出特性要表现为高阻，才能接收信号。<br>
还不如用原理图来的方便。

原帖由 summerxyh 于 2007-2-28 15:29 发表<br>
你这样写好像不行，双向端口若作输入时，其输出特性要表现为高阻，才能接收信号。<br>
还不如用原理图来的方便。 PROCESS(DIRR,DIRW)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;BEGIN<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;IF(DIRR='0')THEN <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR1 &lt;= ADDR2;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR2&lt;="ZZZZZZZZ";<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;ELSIF(DIRW='0')THEN<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR2 &lt;= ADDR1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;ADDR1&lt;="ZZZZZZZZ";<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;END IF;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;END PROCESS;

这样的描述肯定不对，综合的结果大概是2个8位的寄存器。<br>
因为你这里的条件句对于ADDR1 和&nbsp;&nbsp;ADDR2来说都是不完整的，所以会被综合成为寄存器。<br>
<br>
改成这样就可以了。LIBRARY IEEE;<br>
USE IEEE.STD_LOGIC_1164.ALL;<br>
<br>
ENTITY TRIGATE IS<br>
PORT<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;(<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR1:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR2:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; DIRR:IN STD_LOGIC;&nbsp; &nbsp;&nbsp;&nbsp;--控制读时，addr1为输出，addr2为输入<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; DIRW:IN STD_LOGIC&nbsp; &nbsp;&nbsp;&nbsp;--控制读时，addr2为输出，addr1为输入<br>
<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;);<br>
END TRIGATE;<br>
<br>
ARCHITECTURE A OF TRIGATE IS<br>
BEGIN <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbspROCESS(DIRR,DIRW)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;BEGIN<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;IF(DIRR='0')THEN <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR1 &lt;= ADDR2;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR2 &lt;= (others =&gt; 'Z');<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;ELSIF(DIRW='0')THEN<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR2 &lt;= ADDR1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR1 &lt;= (others =&gt; 'Z');<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; ELSE<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR1 &lt;= (others =&gt; 'Z');<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ADDR2 &lt;= (others =&gt; 'Z');<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;END IF;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;END PROCESS;<br>
END A; <br>
[ 本帖最后由 dianzi 于 2007-2-28 17:04 编辑 ]

收下，我验证一下！谢谢大家

斑竹。只记的这么是给addr1附为高阻态，但是忘记是该那个OTHERS到底是怎么解读的了。ADDR1 &lt;= (others =&gt; 'Z');万望不吝赐教。

others&nbsp;&nbsp;是不是在有条件或者选择语句的地方都可以用？<br>
我记得if 是和 else一起用的

ADDR1 &lt;= (others =&gt; 'Z');意思是对ADDR1总线的各位均为高阻，这是一种简写，对位数比较多的时候就比较有用。

原帖由 summerxyh 于 2007-3-1 15:15 发表<br>
ADDR1 &lt;= (others =&gt; 'Z');意思是对ADDR1总线的各位均为高阻，这是一种简写，对位数比较多的时候就比较有用。 说得很对，<br>
<br>
其实你写成&nbsp;&nbsp;ADDR2 &lt;= "'ZZZZZZZZ";&nbsp;&nbsp;也完全一样.

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