各位见谅:<br>
可不可以看看这个程序,我还是修改不对,总是在q+2等地方出错。谢谢了!<br>
library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_arith.all;<br>
use ieee.std_logic_unsigned.all;<br>
entity shiyan36 is<br>
port(cp:in std_logic;<br>
res:in std_logic;<br>
d:in std_logic_vector(2 downto 0);<br>
vt_one,vt_two
ut std_logic);<br>
end shiyan36;<br>
architecture a of shiyan36 is<br>
signal wave1,wave2:std_logic;<br>
signal q:integer;<br>
begin<br>
u1:process(d)<br>
begin<br>
q<=conv_integer(d);<br>
end process;<br>
u2:process(cp,res,q)<br>
variable temp:integer range 0 to 7;<br>
begin<br>
if res='0' then<br>
temp:=0;<br>
elsif rising_edge(cp) then <br>
temp:=temp+1;<br>
case temp is<br>
when 0 to q=> wave1<='0';wave2<='0';<br>
when q to q+2=> wave1<='1';wave2<='0';<br>
when q+2 to q+4 => wave1<='0';wave2<='0';<br>
when q+4 to q+6=> wave1<='0';wave2<='1';<br>
when others=> wave1<='0';wave2<='0';<br>
end case;<br>
end if;<br>
end process;<br>
vt_one<=wave1;<br>
vt_two<=wave2;<br>
end a; |