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LIBRARY IEEE;<br>
USE IEEE.STD_LOGIC_1164.ALL; <br>
<br>
ENTITY test IS<br>
PORT( CLK : IN STD_LOGIC;<br>
TRAG: IN STD_LOGIC;<br>
TRAGOUT: BUFFER STD_LOGIC);<br>
END;<br>
<br>
ARCHITECTURE BHV OF test IS<br>
SIGNAL T_OUT:STD_LOGIC;<br>
BEGIN<br>
PROCESS(CLK,TRAG,TRAGOUT)<br>
BEGIN<br>
IF TRAG'EVENT AND TRAG='1' THEN <br>
T_OUT <= '1'; <br>
END IF;<br>
END PROCESS;<br>
<br>
PROCESS(T_OUT,CLK)<br>
VARIABLE CNT:INTEGER range 0 to 10 := 0;<br>
BEGIN<br>
IF CLK'EVENT AND CLK='0' THEN<br>
IF T_OUT = '1' AND CNT = 10 THEN <br>
CNT := 0; <br>
TRAGOUT <= '0'; <br>
ELSE <br>
CNT := CNT + 1;<br>
TRAGOUT<=T_OUT;<br>
END IF;<br>
END IF;<br>
END PROCESS; <br>
<br>
END;<br>
是这样的效果么 ???????????? |
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