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楼主: longtim

这个verilog程序有何问题?

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ups 发表于 2010-6-28 12:16:35 | 显示全部楼层
你的state定义也不对,它至少要两位才够。这是我改完并通过编译的程序:<br>
<br>
module ludeng(clk,rst,min1,min5,min10,reg_ind,major_red,major_green,minor_red,minor_green);<br>
parameter major_0=0,major_1=1,minor=2;<br>
input clk,rst,reg_ind;<br>
output min1,min5,min10;<br>
output major_red,major_green,minor_red,minor_green;<br>
reg min1,min5,min10;<br>
reg next_state,clr;<br>
reg reg_ind1;<br>
reg[1:0] state;<br>
reg cnt,major_red,major_green,minor_red,minor_green;<br>
<br>
assign reg_ind=reg_ind1;<br>
<br>
always@(posedge clk or posedge rst)<br>
begin <br>
&nbsp;&nbsp;if(rst==1'b1)<br>
&nbsp;&nbsp;state&lt;=major_0;<br>
&nbsp;&nbsp;else state&lt;=next_state;<br>
end<br>
<br>
always@(state or min1 or min5 or min10 or reg_ind)<br>
begin <br>
&nbsp; &nbsp; case(state)<br>
&nbsp; &nbsp; major_0:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; major_green=1'b1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; minor_red=1'b1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;if(min5==1'b1)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; next_state=major_1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;else next_state&lt;=major_0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;end<br>
&nbsp; &nbsp; major_1:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; if((min10==1'b1)||(reg_ind==1'b1))<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;next_state=minor;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; else next_state=major_1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp; minor:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;minor_green=1'b1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;major_red=1'b1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; if(min1==1'b1)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;next_state=major_0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;else next_state=minor;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp; default:<br>
&nbsp; &nbsp; next_state=major_0;<br>
&nbsp; &nbsp; endcase<br>
end<br>
&nbsp;&nbsp;<br>
&nbsp;&nbsp;always@(posedge clk)<br>
&nbsp; &nbsp; begin <br>
&nbsp; &nbsp;&nbsp;&nbsp;if(rst==1'b1)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;cnt=10'h000;<br>
&nbsp; &nbsp;&nbsp; &nbsp; else <br>
&nbsp; &nbsp;&nbsp; &nbsp; if(clr==1'b1)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;cnt=10'h000;<br>
&nbsp; &nbsp;&nbsp; &nbsp; else cnt=cnt+1'b1;<br>
&nbsp; &nbsp; end<br>
<br>
always@(cnt or state)<br>
&nbsp;&nbsp;begin <br>
&nbsp; &nbsp;if((state=major_0)&amp;&amp;(cnt==9'd299))<br>
&nbsp; &nbsp; min5=1'b1;<br>
&nbsp; &nbsp;else min5=1'b0;<br>
&nbsp;&nbsp;end<br>
<br>
always@(cnt or state)<br>
&nbsp;&nbsp;begin <br>
&nbsp; &nbsp; if((state=major_1)&amp;&amp;(cnt==9'd299))<br>
&nbsp; &nbsp;&nbsp; &nbsp;min10=1'b1;<br>
&nbsp; &nbsp; else min10=1'b0;<br>
&nbsp;&nbsp;end<br>
<br>
always@(min1 or min5 or min10)<br>
begin <br>
&nbsp; &nbsp;if(min1||min5||min10)<br>
&nbsp; &nbsp;&nbsp; &nbsp;clr=1;<br>
&nbsp; &nbsp;else clr=0;<br>
end<br>
<br>
always@(rst or state)<br>
&nbsp;&nbsp;begin<br>
&nbsp; &nbsp; if(rst==1)<br>
&nbsp; &nbsp;&nbsp; &nbsp;reg_ind1&lt;=1'b0;<br>
&nbsp; &nbsp; else <br>
&nbsp; &nbsp; if(state==minor)<br>
&nbsp; &nbsp; reg_ind1&lt;=1'b0;<br>
&nbsp;&nbsp;end<br>
<br>
endmodule
inter 发表于 2010-6-28 12:28:41 | 显示全部楼层
我大体上应该没动你的原意,只是改了一些语法错误,希望对你有用而我没白做。
usd 发表于 2010-6-28 12:38:36 | 显示全部楼层
建议你用编译软件检查出错误,并一个个改正
CHANG 发表于 2010-6-28 12:56:28 | 显示全部楼层
好的代码风格便于阅读,容易看出问题,这样别人也有耐心看。
usd 发表于 2010-6-28 14:05:22 | 显示全部楼层
晕倒了<br>
好乱
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