求关于乘法器的vhdl设计设计范例

求关于乘法器的vhdl设计设计范例
乘法器的vhdl设计，不知各位大侠是否有这方面的范例呢？主要是wt和MBA,不知道各位有什么好建议，谢谢啦

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mul4x4 is
port(clk,load:in std_logic;
a,b:in std_logic_vector(3 downto 0);
pout
       
ut std_logic;
dout
       
ut std_logic_vector(7 downto 0));
end mul4x4;
architecture fun of mul4x4 is
component cnt2y
port(clk,load:std_logic;
   pout
       
ut std_logic);
end component;
component reg4b
port(clk,load:std_logic;
ain: in std_logic_vector(3 downto 0);
qut std_logic);
end component;
component switch
port(qin:std_logic;
bin:in std_logic_vector(3 downto 0 );
doutut std_logic_vector(3 downto 0));
end component;
component adder4
port(a,b: in std_logic_vector(3 downto 0);
p: out std_logic_vector(4 downto 0));
end component;
component reg8  
port(clk,load,qi: in std_logic;
din: in std_logic_vector(4 downto 0);
dout: out std_logic_vector(7 downto 0));
end component ;
component outp1  
port(din: in std_logic_vector(7 downto 0);
outp: out std_logic_vector(7 downto 0));
end component;
component dand  
port(al: in std_logic;cl: out std_logic);
end component;


signal r,s,t,z,x: std_logic;
signal ssss: std_logic_vector(7 downto 0);
signal ww: std_logic_vector(4 downto 0);
signal vv: std_logic_vector(3 downto 0);
begin
m1: cnt2y port map( clk=>clk, load=>load, pout=>x);
m2: reg4b port map( clk=>clk, load=>load, ain=>a,q=>r);
m3: switch port map( qin=>r, bin=>b, dout=>vv);
m4: adder4 port map( a=>ssss(7 downto 4),b=>vv, p=>ww);
m5: reg8 port map ( clk=>clk, load=>load, din=>ww, dout=>ssss, qi=>x);
m6: outp1 port map(din=>ssss, outp=>dout);
m7: dand port map(al=>x,cl=>pout);
Endfun;
----------------------------------------------------------adder4(m4)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4 is
port(a,b: in std_logic_vector(3 downto 0);
p: out std_logic_vector(4 downto 0));
end adder4;
architecture bh of adder4 is
begin
process(a,b)
begin
p<=a+b;
end process;
End bh;
--------------------------------------------------------switch(m3)
library ieee;
use ieee.std_logic_1164.all;
entity switch is
port( qin:std_logic;
   bin: in std_logic_vector(3 downto 0);
   dout: out std_logic_vector(3 downto 0));
end switch;
architecture bh of switch is
begin
process(qin,bin)
begin
for I in 0 to 3 loop
dout(I)<=bin(I) and qin;
end loop;
end process;
end bh;
--------------------------------------------------------reg4b(m2)
library ieee;
use ieee.std_logic_1164.all;
entity reg4b is
port( clk,load:std_logic;
  ain: in std_logic_vector(3 downto 0);
   q: out std_logic);
end reg4b;
architecture bh of reg4b is
signal x: std_logic_vector(3 downto 0);
begin
process(clk,load)
begin
if clk'event and clk='1'then
if load='1'then x<=ain;
else x(2 downto 0)<=x(3 downto 1);
end if;
end if;
end process;
q<=x(0);
end bh;

-------------------------------------------------------reg8(m5)
library ieee;
use ieee.std_logic_1164.all;
entity reg8 is
port(clk,qi,load: in std_logic;
din: in std_logic_vector(4 downto 0);
dout: out std_logic_vector(7 downto 0));
end reg8;
architecture bh of reg8 is
signal w: std_logic_vector(7 downto 0);
begin
process(clk,load)
begin
if load='1'then w<="00000000";
elsif clk'event and clk='1'then
if qi='0'then
w(2 downto 0)<=w(3 downto 1);
w(7 downto 3)<=din;
else
w(2 downto 0)<=w(2 downto 0);
w(7 downto 3)<=w(7 downto 3);
end if;
end if;
end process;
dout<=w;
End bh;
-------------------------------------cnt2y(m1)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt2y is
port(clk,load:std_logic;
pout: out std_logic);
end cnt2y;
architecture bh of cnt2y is
signal M:std_logic_vector(2 downto 0);
begin
process(clk,load)
begin
if load='1'then M<="000";
elsif clk'event and clk='1'then
if M<4 then
M<=M+1;
end if;
end if;
end process;
process(load,M)
begin
if load='0' then
if M<4 then
pout<='0';
else
   pout<='1';
end if;
else
pout<='0';
end if;
end process;
end bh;
----------------------------------outp
library ieee;
use ieee.std_logic_1164.all;
entity outp1 is
port(din: in std_logic_vector(7 downto 0);
outp: out std_logic_vector(7 downto 0));
end outp1;
architecture bh of outp1 is
begin
outp<=din;
End bh;
---------------------------------------dand
library ieee;
use ieee.std_logic_1164.all;
entity dand is
port(al: in std_logic;
cl: out std_logic);
end dand;
architecture bh of dand is
begin
cl<=al;
End bh;

楼上的 能再给个32位的例子吗？

都是vhdl实现的！！有没有用原理图实现的？

有用verilog实现的吗

我毕业设计也是乘法器，做阵列乘法器，部分积产生用布思编码，累加用华莱士树。

虽然对我没什么用,但还时谢谢了

仔细看过了

乘法器是由加法器实现的，可以采用超前进位加法器<br>
对被乘数使用booth编码，部分积累加采用华莱士树可以很好的优化乘法器<br>
既可以得到面积优化又可以获得速度上的优化。

华莱士树，恩，其实这些结构都可以上网好好看看，招聘面试很注重基础。<br>
大家以后粘代码的时候最好加上注视