设计一个计时范围为0.01秒～1小时的秒表：

library ieee;
use ieee.std_logic_1164.all;
entity timer is
port(clk:  in std_logic;
   out1: outstd_logic_vector(6 downto 0);
   out2: outstd_logic_vector(6 downto 0);
   contr1: outstd_logic_vector(3 downto 0);//刷新的控制
   contr2: outstd_logic_vector(1 downto 0));//刷新的控制

end entity;
architecture behav of timer is
signal miao1: integer range 0 to 9 ; 1/100秒位
signal miao2: integer range 0 to 9 ;
signal miao3: integer range 0 to 9 ;
signal miao4: integer range 0 to 5 ;
signal flash :integer range 0 to 5;
signal midvar:integer range 0 to 9;
signal fen1: integer range 0 to 9 ;
signal fen2: integer range 0 to 5 ;
signal fmidvar:integer range 0 to 9;
begin
p1:process(clk)
variable div: integer range 0 to 10000;
begin
  if(clk='1' and clk'event)  
  then if(div=10000) then div:=0;
   if(miao1=9) then miao1<=0;
    if(miao2=9) then miao2<=0;
     if(miao3=9) then miao3<=0;
    if(miao4=5)thenmiao4<=0;
     if(fen1=9)then fen1<=0;
      if(fen2=5) then fen2<=0;
      else fen2<=fen2+1;
      end if;
     else fen1<=fen1+1;
     end if;
    else miao4<=miao4+1;
    end if;
    else miao3<=miao3+1;
     end if;
     else miao2<=miao2+1;
    end if;
   else miao1<=miao1+1;
   end if;
  else div:=div+1;
  end if;
end if;  
end process p1;
p2:process(clk)
variable delay :integer range 0 to 100;
begin
if(clk='1' and clk'event)
then if(delay=100)
  thendelay:=0;
  if(flash=5) then flash<=0;
  else flash<=flash+1;
  end if;
  else delay:=delay+1;
  end if;
  case flash is
   when 0=>contr1<="1110";midvar<=miao1;
   when 1=>contr1<="1101";midvar<=miao2;
   when 2=>contr1<="1011";midvar<=miao3;
   when 3=>contr1<="0111";midvar<=miao4;
   when 4=>contr2<="01";fmidvar<=fen1;
   when 5=>contr2<="10";fmidvar<=fen2;
   end case;
  
case midvar is
when 0 =>out1<="0111111";
when 1 =>out1<="0000110";
when 2 =>out1<="1011011";
when 3 =>out1<="1001111";
when 4 =>out1<="1100110";
when 5 =>out1<="1101101";
when 6 =>out1<="1111101";
when 7 =>out1<="0000111";
when 8 =>out1<="1111111";
when 9 =>out1<="1101111";
end case;
case fmidvar is
when 0 =>out2<="0111111";
when 1 =>out2<="0000110";
when 2 =>out2<="1011011";
when 3 =>out2<="1001111";
when 4 =>out2<="1100110";
when 5 =>out2<="1101101";
when 6 =>out2<="1111101";
when 7 =>out2<="0000111";
when 8 =>out2<="1111111";
when 9 =>out2<="1101111";
end case;
end if;
end process p2;
end behav;