verilog3人表决器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--*********************************************
ENTITY majority_voter IS
PORT(SW : IN std_logic_vector(3 DOWNTO 1);
L : OUT std_logic_vector(2 DOWNTO 1));
--L2 is a yellow LED AND L1 is a RED LED
END majority_voter;
--*********************************************
ARCHITECTURE concurrent OF majority_voter IS

BEGIN
  WITH SW SELECT
  L <= "10" WHEN "011",
     "10"WHEN "101",
     "10"WHEN "110",
     "10"WHEN "111",
     "01" WHEN OTHERS;
END concurrent;

what's going on?

什么意思 我英语不好~