|
library IEEE;<br>
use IEEE.STD_LOGIC_1164.ALL;<br>
use IEEE.STD_LOGIC_ARITH.ALL;<br>
use IEEE.STD_LOGIC_UNSIGNED.ALL;<br>
<br>
-- Uncomment the following lines to use the declarations that are<br>
-- provided for instantiating Xilinx primitive components.<br>
-- library UNISIM;<br>
-- use UNISIM.VComponents.all;<br>
<br>
entity lcd913 is<br>
Port ( clk: in std_logic;<br>
rs : out std_logic;<br>
rw : out std_logic;<br>
Enable: out std_logic;<br>
s: out std_logic_vector(7 downto 0));<br>
end lcd913;<br>
architecture Behavioral of lcd913 is<br>
TYPE AD_STATES IS(S0,S1,S2,S3,S4,S5,S8,S9,S10,S11,s12,s13);<br>
SIGNAL CURRENT_STATE,NEXT_STATE:AD_STATES; <br>
signal newclk: std_logic; <br>
--subtype state_type is std_logic_vector(3 downto 0);<br>
--signal current_state:state_type;<br>
--signal next_state:state_type;<br>
--constant s0:state_type:="0000";<br>
--constant s1:state_type:="0001";<br>
--constant s2:state_type:="0010";<br>
--constant s3:state_type:="0011";<br>
--constant s4:state_type:="0100";<br>
--constant s5:state_type:="0101";<br>
--constant s6:state_type:="0110";<br>
--constant s7:state_type:="0111";<br>
--constant s8:state_type:="1000";<br>
--constant s9:state_type:="1001";<br>
--constant s10:state_type:="1010";<br>
--constant s11:state_type:="1011";<br>
begin<br>
<br>
process(clk)<br>
variable count: integer;<br>
begin<br>
if(clk'event and clk='1' )then<br>
count:=count+1;<br>
if count=45000 then <br>
current_state<=next_state;<br>
count:=0;<br>
end if; <br>
end if;<br>
<br>
end process;<br>
<br>
process(current_state)<br>
begin <br>
case current_state is<br>
when s0=><br>
Enable<='1';<br>
rs<='0';<br>
rw<='0';<br>
s<="00110000";<br>
next_state<=s1;<br>
<br>
when s1=><br>
rs<='0';<br>
rw<='0';<br>
s<="00110000";<br>
Enable<='0';<br>
next_state<=s2;<br>
<br>
when s2=><br>
Enable<='1';<br>
rs<='0';<br>
rw<='0';<br>
s<="00110000";<br>
next_state<=s3;<br>
<br>
when s3=><br>
rs<='0';<br>
rw<='0';<br>
s<="00110000";<br>
Enable<='0';<br>
next_state<=s4;<br>
<br>
when s4=><br>
Enable<='1';<br>
rs<='0';<br>
rw<='0';<br>
s<="00001100";<br>
next_state<=s5;<br>
<br>
when s5=><br>
rs<='0';<br>
rw<='0';<br>
s<="00001100";<br>
Enable<='0';<br>
next_state<=s8;<br>
<br>
<br>
<br>
when s8=><br>
Enable<='1';<br>
rs<='0';<br>
rw<='0';<br>
s<="00000110";<br>
next_state<=s9;<br>
when s9=><br>
rs<='0';<br>
rw<='0';<br>
s<="00000110";<br>
Enable<='0';<br>
next_state<=s10;<br>
when s10=><br>
Enable<='1';<br>
rs<='0';<br>
rw<='0';<br>
s<="00100000";<br>
next_state<=s11;<br>
when s11=><br>
rs<='0';<br>
rw<='0';<br>
s<="00100000";<br>
Enable<='0';<br>
next_state<=s12;<br>
when s12=><br>
Enable<='1';<br>
rs<='1';<br>
rw<='0';<br>
s<="00110001";<br>
next_state<=s13;<br>
when s13=><br>
rs<='1';<br>
rw<='0';<br>
s<="00110001";<br>
Enable<='0';<br>
next_state<=s0;<br>
when others=><br>
next_state<=s0;<br>
end case;<br>
end process; <br>
end Behavioral;<br>
<br>
<br>
不知这个合适不.. |
|