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我在做一个BP网络的前向模块。请大家帮我看看错在哪儿?谢谢
# ** Warning: (vsim-3015) E:/bp_btt_sim/ANN_net/ANN_net.v(31): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'b'.
# Region: /tb_ANN_net/ANN_net1/m4
# ** Warning: (vsim-3015) E:/bp_btt_sim/ANN_net/ANN_net.v(32): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'b'.
# Region: /tb_ANN_net/ANN_net1/m5
# ** Warning: (vsim-3015) E:/bp_btt_sim/ANN_net/ANN_net.v(33): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'b'.
# Region: /tb_ANN_net/ANN_net1/m6
# ** Warning: (vsim-3015) E:/bp_btt_sim/ANN_net/ANN_net.v(34): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'b'.
# Region: /tb_ANN_net/ANN_net1/m7
# ** Warning: (vsim-3015) E:/bp_btt_sim/ANN_net/ANN_net.v(35): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'b'.
# Region: /tb_ANN_net/ANN_net1/m8
# ** Warning: (vsim-3015) E:/bp_btt_sim/ANN_net/ANN_net.v(36): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'b'.
# Region: /tb_ANN_net/ANN_net1/m9
==================================================================================================
代码1:
乘法器:
module mult_16x16(a,b,c,clk,en);
input clk,en;
input [15:0] a;
input [15:0] b;
output [15:0] c;
reg [15:0] c;
reg [31:0] r_out;
always @(posedge clk )
if(!en)
begin
r_out = a*b;
c<=r_out[23:8];
end
else
c<=c;
endmodule
==================================================================================================
代码2:
加法器:
module note_acc(a,b,c,d,u,clk,en);
input clk,en; //时钟信号和低电平有效的使能信号
input [0:15] a,b,c,d;//三个神经元输入信号和一个阈值
output[0:15] u;
reg[0:15] u; //一个输出端16位寄存器
always @(posedge clk)
begin
if(!en)
begin u<=a+b+c-d; end //en为低电平时 u=a+b+c-d
else
begin u<=u; end //en为其他状态时输出锁存
end
endmodule
==================================================================================================
代码3:
sigmoid函数:
module sigmoid(u,f,clk,en);
input clk,en; //时钟信号和低电平有效的使能信号
input[0:15] u; //累加器的累加结果
output[0:15] f; //激活函数的输出值(神经元的输出结果)
reg[0:15] f;
always@(posedge clk)
begin if(!en) f<=sigmoid(u); //en为低电平时调用sigmiod函数
else f<=f; //en为高电平或其他状态时输出锁存
end
function[0:15] sigmoid; //定义函数
input[0:15] x;
begin
if(x<5742) //开区间内直线定义
sigmoid=x/2+2347;
else if(5742<x<9640)
sigmoid=x*13/16+553;
else if(9640<x<23000)
sigmoid=x*19/16-3062;
else if(23000<x<27414)
sigmoid=x*13/16+5562;
else if(27414<x)
sigmoid=x/2+14129;
else if(x==5742) //区间端点值定义
sigmoid=5218;
else if(x==9640)
sigmoid=8385;
else if(x==23000)
sigmoid=24250;
else if(x==27414)
sigmoid=27836;
else sigmoid=0; //其他输入情况下输出0
end
endfunction
endmodule
==================================================================================================
代码4:
前向模块:
module ANN_net(x1,x2,x3,
w11,w12,w13,w21,w22,w23,w31,w32,w33,
w211,w212,w213,w221,w222,w223,w231,w232,w233,v1,v2,v3,
sita4,sita5,sita6,sita7,sita8,sita9,sita10,y,sig4,sig5,sig6,z41,z42,z43,
clk,en);
input clk,en; //时钟信号和低电平有效的使能信号
input[0:15] x1,x2,x3; //神经网络的三个输入变量
output[0:15] y,sig4,sig5,sig6,z41,z42,z43; //网络内各神经元的输出
//下面输入神经元之间的链接权值和阈值
input[0:15] w11,w12,w13,w21,w22,w23,w31,w32,w33,
w211,w212,w213,w221,w222,w223,w231,w232,w233,
v1,v2,v3,
sita4,sita5,sita6,sita7,sita8,sita9,sita10;
//下面是前向网络内部模块间的连接线
wire[0:15] z11,z12,z13,z14,z15,z16,z17,z18,z19,
z21,z22,z23,z24,z25,z26,z27,z28,z29,
z31,z32,z33,z34,z35,z36,z37,z38,z39,
u4,u5,u6,u7,u8,u9,u10,
z41,z42,z43,
z51,z52,z53;
//输入层3个结点
//引用九个集成乘法器,输入层结点的输出乘以权值
mult_16x16 m1(.a(x1),.b(w11),.c(z11),.clk(clk),.en(en));
mult_16x16 m2(.a(x1),.b(w12),.c(z12),.clk(clk),.en(en));
mult_16x16 m3(.a(x1),.b(w13),.c(z13),.clk(clk),.en(en));
mult_16x16 m4(.a(x2),.b(w14),.c(z14),.clk(clk),.en(en));
mult_16x16 m5(.a(x2),.b(w15),.c(z15),.clk(clk),.en(en));
mult_16x16 m6(.a(x2),.b(w16),.c(z16),.clk(clk),.en(en));
mult_16x16 m7(.a(x3),.b(w17),.c(z17),.clk(clk),.en(en));
mult_16x16 m8(.a(x3),.b(w18),.c(z18),.clk(clk),.en(en));
mult_16x16 m9(.a(x3),.b(w19),.c(z19),.clk(clk),.en(en));
//引用三个累加器,第一隐含层结点输入累加,再减去阈值
note_acc n4(.a(z11),.b(z14),.c(z17),.d(sita4),.u(u4),.clk(clk),.en(en));
note_acc n5(.a(z12),.b(z15),.c(z18),.d(sita5),.u(u5),.clk(clk),.en(en));
note_acc n6(.a(z13),.b(z16),.c(z19),.d(sita6),.u(u6),.clk(clk),.en(en));
//引用三个激活函数模块,累加之后经过激活函数处理,得第一隐含层输出
sigmoid f4(.u(u4),.f(sig4),.clk(clk),.en(en));
sigmoid f5(.u(u5),.f(sig5),.clk(clk),.en(en));
sigmoid f6(.u(u6),.f(sig6),.clk(clk),.en(en));
//第一隐含层3个结点输出
//引用九个集成硬件乘法器,第一隐含层结点的输出乘以权值
mult_16x16 m10(.a(sig4),.b(w211),.c(z31),.clk(clk),.en(en));
mult_16x16 m11(.a(sig4),.b(w212),.c(z32),.clk(clk),.en(en));
mult_16x16 m12(.a(sig4),.b(w213),.c(z33),.clk(clk),.en(en));
mult_16x16 m13(.a(sig5),.b(w221),.c(z34),.clk(clk),.en(en));
mult_16x16 m14(.a(sig5),.b(w222),.c(z35),.clk(clk),.en(en));
mult_16x16 m15(.a(sig5),.b(w223),.c(z36),.clk(clk),.en(en));
mult_16x16 m16(.a(sig6),.b(w231),.c(z37),.clk(clk),.en(en));
mult_16x16 m17(.a(sig6),.b(w232),.c(z38),.clk(clk),.en(en));
mult_16x16 m18(.a(sig6),.b(w233),.c(z39),.clk(clk),.en(en));
//引用三个累加器,第二隐含层结点输入累加,再减去阈值
note_acc n7(.a(z31),.b(z34),.c(z37),.d(sita7),.u(u7),.clk(clk),.en(en));
note_acc n8(.a(z32),.b(z35),.c(z38),.d(sita8),.u(u8),.clk(clk),.en(en));
note_acc n9(.a(z33),.b(z36),.c(z39),.d(sita9),.u(u9),.clk(clk),.en(en));
//引用三个函数激活模块,累加之后经过激活函数处理,得第二隐含层输出
sigmoid f7 (.u(u7),.f(z41),.clk(clk),.en(en));
sigmoid f8 (.u(u8),.f(z42),.clk(clk),.en(en));
sigmoid f9 (.u(u9),.f(z43),.clk(clk),.en(en));
//引用三个集成硬件乘法器,第二隐含层的输出乘权值
mult_16x16 m19(.a(z41),.b(v1),.c(z51),.clk(clk),.en(en));
mult_16x16 m20(.a(z42),.b(v2),.c(z52),.clk(clk),.en(en));
mult_16x16 m21(.a(z43),.b(v3),.c(z53),.clk(clk),.en(en));
//输出端引用一个累加器,输出层结点输入累加,再减去阈值
note_acc n10(.a(z51),.b(z52),.c(z53),.d(sita10),.u(u10),.clk(clk),.en(en));
//输出端引用一个激活函数模块,累加结果经过激活函数处理后得到网络输出
sigmoid f10(.u(u10),.f(y),.clk(clk),.en(en));
endmodule
==================================================================================================
测试文件
module tb_ANN_net;
reg clk,en;
reg[0:15] x1,x2,x3;
reg[0:15] w11,w12,w13,w21,w22,w23,w31,w32,w33,
w211,w212,w213,w221,w222,w223,w231,w232,w233,
v1,v2,v3,
sita4,sita5,sita6,sita7,sita8,sita9,sita10;
wire[0:15] y,sig4,sig5,sig6,z41,z42,z43;
ANN_net ANN_net1(.x1(x1),.x2(x2),.x3(x3),
.w11(w11),.w12(w12),.w13(w13),.w21(w21),.w22(w22),.w23(w23),
.w31(w31),.w32(w32),.w33(w33),.w211(w211),.w212(w212),
.w213(w213),.w221(w221),.w222(w222),.w223(w223),.w231(w231),
.w232(w232),.w233(w233),.v1(v1),.v2(v2),.v3(v3),
.sita4(sita4),.sita5(sita5),.sita6(sita6),.sita7(sita7),
.sita8(sita8),.sita9(sita9),.sita10(sita10),.y(y),.sig4(sig4),.sig5(sig5),
.sig6(sig6),.z41(z41),.z42(z42),.z43(z43),
.clk(clk),.en(en));
initial
begin
clk=0;
forever #50 clk=!clk;
end
initial
begin
x1=16'd100;
x2=16'd100;
x3=16'd100;
w11=16'd55;
w12=16'd55;
w13=16'd55;
w21=16'd55;
w22=16'd55;
w23=16'd55;
w31=16'd55;
w32=16'd55;
w33=16'd55;
w211=16'd55;
w212=16'd55;
w213=16'd55;
w221=16'd55;
w222=16'd55;
w223=16'd55;
w231=16'd55;
w232=16'd55;
w233=16'd55;
v1=16'd55;
v2=16'd55;
v3=16'd55;
sita4=16'd45;
sita5=16'd45;
sita6=16'd45;
sita7=16'd45;
sita8=16'd45;
sita9=16'd45;
sita10=16'd45;
en=0;
end
endmodule
请帮我看看错在哪儿 谢谢 |
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