请求高手援助，

源程序：library ieee;
use ieee.std_logic_1164.all;
package state_pack is
type state is(qa,qb);
end state_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.state_pack.all;
entity zhukong is
port(start,clk,t:in std_logic;
      d,b:in integer range 0 to 13;
en1,en2, reset, clr,en3ut std_logic;
cut integer range 0 to 13;
diut integer range 0 to 9);
end zhukong;       
architecture a of zhukong is
signal current_state:state:=qa;
begin
process
variable var:integer range 0 to 13;
begin
wait until clk='1' and clk'event;
if start='1' then
current_state<=qa;
c<=b; en1<='0'; reset<='1';en2<='0';clr<='1';en3<='0';di<=0;
else
case current_state is
when  qa=> if d=0 then
current_state<=qa; en1<='0';en2<='1';clr<='0';c<=0;reset<='0';di<=0;
else  current_state<=qb; var:=d; en2<='0';
此段程序为售货机在初始状态时的信号输出，当d输入信号时进入对比程序。
current_state<=qa; en1<='0';en2<='1';clr<='0';c<=0;reset<='0';di<=0;
else  current_state<=qb; var:=d; en2<='0';
end if;
when qb=>
if t='0'and var<=b then
current_state<=qa;en1<='0';c<=b-var;clr<='1';reset<='1';en3<='1';di<=b-var;
elsif t='0' and b<var then
en1<='1'; c<=0 ; clr<='0'; reset<='0';en3<='0';di<=0;
elsif t='1'and b<var then
current_state<=qa;en1<='0';c<=b;clr<='1';reset<='1';en3<='0';di<=0;
elsif t='1' and b>=var then
current_state<=qa;en1<='0'; c<=b-var;clr<='1';reset<='1';en3<='1';di<=b-var;
end if;
end case;
end if;
end process;
end a;
大家看看那里出问题

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