异或,结果为0说明奇数,结果为1说明偶数
entiry odd is
port(datain: in std_logic_vector(7 downto 0);
dataout: out std_logic
);
end odd;
architecture behave of odd is
signal temp: std_logic;
begin
process(datain)
begin
temp<='1';
for i in 0 to 7 loop
temp<=temp xor data(i);
end loop;
dataout<=temp;
end process
end behave;